Engineering Questions with Answers - Multiple Choice Questions

Microprocessors MCQ’s – Register Organisation of 80386 -2

1 - Question

The 32-bit control register, that is used to hold global machine status, independent of the executed task is
a) CR0
b) CR2
c) CR3
d) All of the mentioned

View Answer

Answer: d
Explanation: The 80386 has three 32-bit control registers CR0, CR2 and CR3, to hold global machine status, independent of the executed task.




2 - Question

The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) All of the mentioned

View Answer

Answer: d
Explanation: The 80386 supports four types of descriptor tables. They are, GDT, IDT, LDT and TSS.




3 - Question

 The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR

View Answer

Answer: a
Explanation: The GDTR and IDTR are known as system address registers.




4 - Question

Which of the following is a system segment register?
a) GDTR
b) LDTR
c) IDTR
d) None of the mentioned

View Answer

Answer: b
Explanation: The LDTR and TR are known as system segment registers.




5 - Question

The test register(s) that is provided by 80386 for page caching is
a) test control registers
b) page cache registers
c) test control and test status registers
d) test control and page cache registers

View Answer

Answer: c
Explanation: Two test registers are provided by 80386 for page caching, namely test control and test status registers.




6 - Question

Among eight debug registers, DR0-DR7, the registers that are reserved by Intel are
a) DR0, DR1, DR2
b) DR4, DR5
c) DR1, DR4
d) DR5, DR6, DR7

View Answer

Answer: b
Explanation: Out of the eight debug registers, the two registers DR4 and DR5 are Intel reserved.




7 - Question

The registers that are used to store four program controllable break point addresses are
a) DR5-DR7
b) DR0-DR1
c) DR6-DR7
d) DR0-DR3

View Answer

Answer: d
Explanation: The initial four registers, DR0-DR3 store four program controllable break point addresses.




8 - Question

The register DR6 hold
a) break point status
b) break point control information
c) break point status and break point control information
d) none of the mentioned

View Answer

Answer: a
Explanation: The registers DR6 and DR7 respectively hold break point status and break point control information.




9 - Question

The flag bits that indicate the privilege level of current IO operations are
a) Virtual mode flag bits
b) IOPL flag bits
c) Resume flag bits
d) None of the mentioned

View Answer

Answer: b
Explanation: The IOPL flag bits indicate the privilege level of current IO operations.




10 - Question

The registers that are not available for programmers are
a) data and address registers
b) instruction pointers
c) segment descriptor registers
d) flag registers

View Answer

Answer: c
Explanation: The segment descriptor registers of 80386 are not available for programmers, rather, they are internally used to store the descriptor information.

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