Engineering Questions with Answers - Multiple Choice Questions
Microprocessors MCQ – Programmable DMA Interface 8237 -2
1 - Question
Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned
View Answer
Answer: d
Explanation: In the request register, each bit is set or reset under program control or is cleared upon generation of a TC or an external EOP.
2 - Question
The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register
View Answer
Answer: b
Explanation: The temporary register holds the data during memory to memory data transfers. After the completion of the transfer operation, the last word transferred remains in the temporary register, until it is cleared by a reset operation.
3 - Question
The register that keeps track of all the DMA channel pending requests and status of their terminal counts is
a) mask register
b) request register
c) status register
d) count register
View Answer
Answer: c
Explanation: The status register keeps track of all the DMA channel pending requests, and status of their terminal counts. These are cleared upon reset.
4 - Question
The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET
View Answer
Answer: d
Explanation: A high on the reset pin clears the command, status, request and temporary registers, and also clears the internal first/last flipflop.
5 - Question
The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3
View Answer
Answer: a
Explanation: DREQ0 has the highest priority while DREQ3 has the lowest one. The priorities of the DREQ lines is programmable.
6 - Question
When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned
View Answer
Answer: c
Explanation: If 8237 is in idle state, then CPU may program it in this state.
7 - Question
To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned
View Answer
Answer: c
Explanation: A memory to memory transfer is a two cycle operation and requires a read from and write-to memory cycle, to complete each DMA transfer.
8 - Question
In demand transfer mode of 8237, the device stops data transfer when
a) a TC (terminal count) is reached
b) an external EOP (active low) is detected
c) the DREQ signal goes inactive
d) all of the mentioned
View Answer
Answer: d
Explanation: In demand transfer mode, the device continues transfers till a TC is reached or an external EOP is detected or the DREQ signal goes inactive.
9 - Question
The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode
View Answer
Answer: b
Explanation: In single mode, the device transfers only one byte per request. For each transfer, the DREQ must be active until the DACK is activated.
10 - Question
The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode
View Answer
Answer: c
Explanation: To perform the transfer of a block of data from one set of a memory address to another one, this transfer mode is used.
11 - Question
Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned
View Answer
Answer: b
Explanation: Using master clear command, all the internal registers of 8237 are cleared, while all the bits of the mask register are set.