Engineering Questions with Answers - Multiple Choice Questions
Microprocessors MCQ – Paging
1 - Question
The advantage of pages in paging is
a) no logical relation with program
b) no need of entire segment of task in physical memory
c) reduction of memory requirement for task
d) all of the mentioned
View Answer
Answer: d
Explanation: The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time. Only a few pages of the segments, which are required currently for the execution, need to be available in the physical memory.
2 - Question
The size of the pages in the paging scheme is
a) variable
b) fixed
c) both variable and fixed
d) none
View Answer
Answer: b
Explanation: The paging divides the memory into fixed size pages.
3 - Question
To convert linear addresses into physical addresses, the mechanism that the paging unit uses is
a) linear conversion mechanism
b) one level table mechanism
c) physical conversion mechanism
d) two level table mechanism
View Answer
Answer: d
Explanation: The paging unit of 80386 uses a two level table mechanism, to convert the linear addresses provided by the segmentation unit, into physical addresses.
4 - Question
The control register that stores the 32-bit linear address, at which the previous page fault is detected is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: c
Explanation: The control register, CR2, is used to store the 32-bit linear address, at which the previous page fault is detected.
5 - Question
Which of the following is not a component of paging unit?
a) page directory
b) page descriptor base register
c) page table
d) page
View Answer
Answer: b
Explanation: The paging unit handles every task in terms of three components namely page directory, page table and the page itself.
6 - Question
The control register that is used as page directory physical base address register is
a) CR0
b) CR1
c) CR2
d) CR3
View Answer
Answer: d
Explanation: The control register, CR3, is used as page directory physical base address register, to store the physical starting address of the page directory.
7 - Question
The bits of CR3, that are always zero are
a) higher 4 bits
b) lower 8 bits
c) higher 10 bits
d) lower 12 bits
View Answer
Answer: d
Explanation: The lower 12 bits of CR3 are always zero to ensure the page size aligned with the directory.
8 - Question
Each directory entry in page directory is maximum of
a) 2 bytes
b) 4 bytes
c) 8 bytes
d) 16 bytes
View Answer
Answer: b
Explanation: Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.
9 - Question
The size of each page table is of
a) 2 Kbytes
b) 2 bytes
c) 4 Kbytes
d) 4 bytes
View Answer
Answer: c
Explanation: Each page table is of 4 Kbytes in size, and may contain a maximum of 1024 entries.
10 - Question
The dirty bit(D) is set, before which operation is carried out
a) write
b) read
c) initialization
d) none of the mentioned
View Answer
Answer: a
Explanation: The dirty bit (D) is set before a write operation to the page is carried out.
11 - Question
The bit that is undefined for page directory entries is
a) P-bit
b) A-bit
c) D-bit
d) All of the mentioned
View Answer
Answer: c
Explanation: The D-bit is undefined for page directory entries.
12 - Question
The bit that is used for providing protection is
a) User/Supervisor bit
b) Read bit
c) Write bit
d) all of the mentioned
View Answer
Answer: d
Explanation: The User/Supervisor (U/S) bit and Read/Write (R/W) bit are used to provide protection.
13 - Question
The storage of 32 recently accessed page table entries to optimize the time, is known as
a) page table
b) page descriptor base register
c) page table cache
d) none of the mentioned
View Answer
Answer: c
Explanation: To optimize the considerable time taken for conversion, a page table cache is provided, which stores the 32 recently accessed page table entries.
14 - Question
The page table cache is also known as
a) page table storage
b) storage buffer
c) translation look aside buffer
d) all of the mentioned
View Answer
Answer: c
Explanation: The page table cache is also known as translation look aside buffer.