Engineering Questions with Answers - Multiple Choice Questions
MCQs on TIMER_A
All channels within Timer_A share the same timer block?
c) cant be said
d) depends on the conditions
Explanation: There is only one TAR in Timer_A so all of its channels share the same timer block.
Timer_A has _________
a) RTC module in it
b) Compare/ capture channel
c) Communication channel
d) Converter channel
Explanation: Timer_A has compared/ capture channel inbuilt inside it.
TACLK and INCLK are _________
a) internally generated clock pulses
b) externally fed clock pulses
c) of no use in Timer_A
d) very slow
Explanation: TACLK and INCLK clock pulses are the externally fed pulses that are required by the Timer_A.
In continuous mode of the counter _________
a) counter moves from 0000-ffff
b) counter moves from ffff-0000-ffff
c) counter moves from 0000-ffff and then again returns to 0
d) all of the mentioned
Explanation: In a continuous mode of the counter, the counter firstly increases from 0000-ffff, then after this value the roll over condition comes and it again gets started from 0000. This particular mode is very useful for capturing inputs.
TACLR bit in TACTL _________
a) clear the interrupt flag
b) clear the status flags
c) clear the count in TAR
d) all of the mentioned
Explanation: TACLR bit in TACTL clears the count in the TAR.
TAxCCTLn is a _________
a) set of 2 bits used for selecting the mode of operation of the timer
b) a register of 8 bits used for giving the count to the timer
c) a register of 16 bits used to select the compare/capture channel of the Timer_Ax
d) a register of 16 bits used to cause the timer interrupt
Explanation: TAxCCTLn is a register of 16 bits used to select the compare/capture channel of the Timer_Ax.
CCI1B comes from _________
Explanation: CCI1B comes from CAOUT.
Which of the following parameters are given by the TAxCCRn?
a) Capture/compare input. The selected input signal can be read by this bit
b) Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read from this bit
c) Holds the data for the comparison to the timer value in the Timer_A Register, TAR
d) None of the mentioned
Explanation: Compare mode: TAxCCRn holds the data for the comparison to the timer value in the Timer_A Register, TAR.
Capture mode: The Timer_A Register, TAR, is copied into the TAxCCRn register when capture is performed.