Engineering Questions with Answers - Multiple Choice Questions
MCQs on Specification
1 - Question
MCQs on Introduction to VHDL
Which of the following language can describe the hardware?
a) C
b) C++
c) JAVA
d) VHDL
View Answer
Explanation: The VHDL is the hardware description language which describes the hardware whereas the C, C++ and JAVA are software languages.
2 - Question
What do VHDL stand for?
a) Verilog hardware description language
b) VHSIC hardware description language
c) very hardware description language
d) VMEbus description language
View Answer
Explanation: VHDL is the VHSIC(very high speed integrated circuit) hardware description language which was developed by three companies, IBM, Intermetrics and Texas Instruments and the first version of the VHDL is established in the year 1984 and later on the VHDL is standardised by the IEEE.
3 - Question
What does VHSIC stand for?
a) very high speed integrated chip
b) very high sensor integrated chip
c) Verilog system integrated chip
d) Verilog speed integrated chip
View Answer
Explanation: The VHSIC stands for very high speed integrated chip and VHDL was designed in the context of the VHSIC, developed by the department of defence in the US. advertisement
4 - Question
Each unit to be modelled in a VHDL design is known as
a) behavioural model
b) design architecture
c) design entity
d) structural model
View Answer
Explanation: Each unit to be modelled in a VHDL design is known as the design entity or the VHDL entity. There are two types of ingredients are used. These are the entity declaration and the architecture declaration.
5 - Question
Which of the following are capable of displaying output signal waveforms resulting from stimuli applied to the inputs?
a) VHDL simulator
b) VHDL emulator
c) VHDL debugger
d) VHDL locater
View Answer
Explanation: The VHDL simulator is capable of displaying the output signal waveforms which results from the stimuli or trigger applied to the input.
6 - Question
Which of the following describes the connections between the entity port and the local component?
a) port map
b) one-to-one map
c) many-to-one map
d) one-to-many maps
View Answer
Explanation: The port map describes the connection between the entity port and the local component. The component is declared by component declaration and the entity ports are mapped with the port mapping.
7 - Question
Who proposed the CSA theory?
a) Russell
b) Jacome
c) Hayes
d) Ritchie
View Answer
Explanation: The CSA theory is proposed by Hayes and this theory is based on the systematic way of building up value sets.
8 - Question
Which of the following is a systematic way of building up value sets?
a) CSA theory
b) Bayes theorem
c) Russell’s power mode;
d) first power model
View Answer
Explanation: The CSA theory is proposed by Hayes. The theory is based on the systematic way of building up value sets, that is the electronics design system uses a variety of value sets, like 2, 3 etc. The goal of developing discrete value sets is to avoid the problems of solving network equations.
9 - Question
Which of the following is an abstraction of the signal impedance?
a) level
b) strength
c) size
d) nature
View Answer
Explanation: The systems contain electrical signals of different strengths and it needs to compute the strength and the logic level resulting from a connection of two or more sources of electrical signals. The strength is the abstraction of the signal impedance.
10 - Question
Which of the following is an abstraction of the signal voltage?
a) level
b) strength
c) nature
d) size
View Answer
Explanation: Most of the systems contain electrical signals of different strengths and levels. The level of the signal is the abstraction of the signal voltage and the strength is the abstraction of the signal impedance.
11 - Question
MCQs on Introduction to VHDL-II
How many kinds of wait statements are available in the VHDL design?
a) 3
b) 4
c) 5
d) 6
View Answer
Explanation: There are four kinds of wait statements. These are wait on, wait for, wait until and wait.
12 - Question
Which wait statement does follow a condition?
a) wait for
b) wait until
c) wait
d) wait on
View Answer
Explanation: The wait until follows a condition. The condition may be an arithmetic or logical one and the wait for statement follows time duration, it might be in microseconds or nanoseconds or any other time unit. Similarly, the wait on statement follows a signal list and the wait statement suspends indefinitely.
13 - Question
Which wait statement does follow duration?
a) wait for
b) wait
c) wait until
d) wait on
View Answer
Explanation: The wait for statement follows time duration, it might be in microseconds or nanoseconds or any other time unit. advertisement
14 - Question
Which of the following is a C++ class library?
a) C++
b) C
c) JAVA
d) SystemC
View Answer
Explanation: System C is a C++ class library which helps in solving the behavioural, resolution, simulation time problems.
15 - Question
Which model of SystemC uses floating point numbers to denote time?
a) SystemC 1.0
b) SystemC 2.0
c) SystemC 3.0
d) SystemC 4.0
View Answer
Explanation: The SystemC includes several models of the time units. SystemC 1.0 uses floating point numbers which denote time.
16 - Question
Which model of SystemC uses the integer number to define time?
a) SystemC 1.0
b) SystemC 2.0
c) SystemC 3.0
d) SystemC 4.0
View Answer
Explanation: The SystemC includes several models of the time. System 2.0 is an integer model to define time and this model also supports physical units such as microseconds, nanoseconds, picoseconds etc.
17 - Question
Which model of the SystemC helps in the communication purpose?
a) SystemC 2.0
b) SystemC 3.0
c) SystemC 1.0
d) SystemC 4.0
View Answer
Explanation: The SystemC 2.0 provides the channel port and interface ports for the communication purpose.
18 - Question
Which C++ class is similar to the hardware description language like VHDL?
a) SystemC
b) Verilog
c) C
d) JAVA
View Answer
Explanation: The SystemC is a C++ class which is similar to the hardware description languages like VHDL and Verilog. The execution and simulation time in the SystemC is almost similar to the VHDL.
19 - Question
What does ESL stand for?
a) EEPROM system level
b) Electronic-system level
c) Electrical system level
d) Electron system level
View Answer
Explanation: The ESL is electronic-system level and the SystemC is associated with the ESL and TLM. The SystemC is also applied to the architectural exploration, performance modelling, software development and so on.
20 - Question
What to TLM stand for?
a) transfer level modelling
b) triode level modelling
c) transaction level modelling
d) transistor level modelling
View Answer
Explanation: The TLM is transaction-level modelling and the SystemC is associated with the ESL and TLM.
21 - Question
MCQs on Verilog and System Verilog in Embedded System
Which of the following is standardised as IEEE 1364?
a) C
b) C++
c) FORTRAN
d) Verilog
View Answer
Explanation: The Verilog is a hardware description language which was developed for modelling hardware and electronic devices. This was later standardised by IEEE standard 1364.
22 - Question
Who developed the Verilog?
a) Moorby
b) Thomas
c) Russell and Ritchie
d) Moorby and Thomson
View Answer
Explanation: The Verilog is a hardware description language which was developed by Moorby and Thomson in 1991 and it was standardised as IEEE standard 1364. The Verilog is modelled for the electronics devices.
23 - Question
Which versions of the Verilog is known as System Verilog?
a) Verilog version 3.0
b) Verilog version 1.0
c) Verilog version 1.5
d) Verilog version 4.0
View Answer
Explanation: The Verilog versions 3.0 and 3.1 is called as the System Verilog. These include several extensions to the Verilog version 2.0. advertisement
24 - Question
Which of the following is a Verilog version 1.0?
a) IEEE standard 1394-1995
b) IEEE standard 1364-1995
c) IEEE standard 1394-2001
d) IEEE standard 1364-2001
View Answer
Explanation: The IEEE standard 1364-1995 is the first version of the Verilog and IEEE standard 1394-2001 is the Verilog version 2.0.
25 - Question
Which of the following provides multiple-valued logic with eight signal strength?
a) Verilog
b) VHDL
c) C
d) C++
View Answer
Explanation: The Verilog supports the multiple-valued logic with eight different signal strength but Verilog is less flexible compared to the VHDL, that is, it allows the hardware entities to be instantiated in loops which help to build up a structural description.
26 - Question
Which of the following is a superset of Verilog?
a) Verilog
b) VHDL
c) System Verilog
d) System VHDL
View Answer
Explanation: The System Verilog is a superset of the Verilog. But later on, System Verilog and Verilog has merged into a new IEEE standard 1800-2009.
27 - Question
Which hardware description language is more flexible?
a) VHDL
b) Verilog
c) C
d) C++
View Answer
Explanation: The Verilog is less flexible compared to the VHDL, that is, it allows the hardware entities to be instantiated in loops which help to build up a structural description. But Verilog, on the other hand, focuses more on the built-in features.
28 - Question
Which of the following provide more features for transistor-level descriptions?
a) C++
b) C
c) VHDL
d) Verilog
View Answer
Explanation: The Verilog offers more features than the VHDL but VHDL is more flexible compared to the Verilog. The Verilog can provide transistor-level descriptions but the VHDL cannot provide this description.
29 - Question
Which hardware description language is popular in the US?
a) System Verilog
b) System log
c) Verilog
d) VHDL
View Answer
Explanation: Verilog and VHDL are almost similar in their characteristics and have a similar number of users. The VHDL is more popular in Europe whereas Verilog is more popular in the US.
30 - Question
Which hardware description language is more popular in Europe?
a) VHDL
b) System log
c) Verilog
d) C
View Answer
Explanation: The Verilog and VHDL are hardware description language and these are similar in their characteristics and have a similar number of users. The VHDL is more popular in Europe. The Verilog is more popular in the US.
31 - Question
MCQs on Levels of Hardware Modelling
Which of the following is an analogue extension of the VHDL?
a) VHDL-AMS
b) System VHDL
c) Verilog
d) System Verilog
View Answer
Explanation: The VHDL-AMS is the extension of the VHDL and this includes the analogue and mixed behaviour of the signals.
32 - Question
Which of the following support the modelling partial differentiation equation?
a) gate level
b) algorithmic level
c) system level
d) switch level
View Answer
Explanation: There are a variety of levels for designing the embedded systems and each level has its own language. The system level is one such kind which has many peculiarities with respect to the other levels. The system model denotes the entire embedded system and includes the mechanical as well as the information processing aspects. This also supports the modelling of the partial differential equations, which is a key requirement in the modelling.
33 - Question
Which level simulates the algorithms that are used within the embedded systems?
a) gate level
b) circuit level
c) switch level
d) algorithmic level
View Answer
Explanation: The algorithmic level simulates the algorithm which is used within in the embedded system. advertisement
34 - Question
Which level model components like ALU, memories registers, muxes and decoders?
a) switch level
b) register-transfer level
c) gate level
d) circuit level
View Answer
Explanation: The register-transfer level modelling models all the components like the arithmetic and logical unit(ALU), memories, registers, muxes, decoders etc and this modelling is always cycled truly.
35 - Question
Which of the following is the most frequently used circuit-level model?
a) SPICE
b) VHDL
c) Verilog
d) System Verilog
View Answer
Explanation: The SPICE is simulation program with integrated circuit emphasis, which is a frequently used circuit-level in the early days. It is used to find the behavior and the integrity of the circuit.
36 - Question
Which model includes geometric information?
a) switch-level model
b) layout model
c) gate level model
d) register-transfer level
View Answer
Explanation: The layout reflects the actual circuit model. It includes the geometric information and cannot be simulated directly since it does not provide the information regarding the behavior.
37 - Question
Which model cannot simulate directly?
a) circuit level model
b) switch-level model
c) gate level model
d) layout model
View Answer
Explanation: The layout model reflects the actual circuit model and this includes the geometric information and this model cannot be simulated directly because it does not provide the information regarding the behavior.
38 - Question
Which of the following models the components like resistors, capacitors etc?
a) register-transfer level
b) layout model
c) circuit level model
d) switch-level model
View Answer
Explanation: The circuit-level model simulation is used for the circuit theory and its components such as the resistors, inductors, capacitors, voltage sources, current sources. This simulation also involves the partial differential equations.
39 - Question
Which model uses transistors as their basic components?
a) switch model
b) gate level
c) circuit level
d) layout model
View Answer
Explanation: The switch model can be used in the simulation of the transistors since the transistor is the very basic component in a switch. It is capable of reflecting bidirectional transferring of the information.
40 - Question
Which model is used to denote the boolean functions?
a) switch level
b) gate level model
c) circuit level
d) layout model
View Answer
Explanation: The gate level model is used to denote the boolean functions and the simulation only consider the behaviour of the gate.
41 - Question
Which model is used for the power estimation?
a) gate-level model
b) layout model
c) circuit model
d) switch model
View Answer
Explanation: The gate level model is used to denote the boolean functions and the simulation only consider the behaviour of the gate. This model is also useful in the power estimation since it provides accurate information about the signal transition probabilities.
42 - Question
In which model, the effect of instruction is simulated and their timing is not considered?
a) gate-level model
b) circuit model
c) coarse-grained model
d) layout model
View Answer
Explanation: The coarse-grained model is a kind of the instruction set level modelling in which only the effect of instruction is simulated and the timing is not considered. The information which is provided in the manual is sufficient for this type of modelling.
43 - Question
Which models communicate between the components?
a) transaction level modelling
b) fine-grained modelling
c) coarse-grained modelling
d) circuit level model
View Answer
Explanation: The transaction level modelling is a type of instruction set level model. This modelling helps in the modelling of components which is used for the communication purpose. It also models the transaction, such as read and writes cycles.
44 - Question
Which of the following has a cycle-true set of simulation?
a) switch-level model
b) layout model
c) circuit-level
d) fine-grained model
View Answer
Explanation: The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.