Engineering Questions with Answers - Multiple Choice Questions

MCQs on Signal Descriptions of 80286

1 - Question

The 80286 is available in the package as
a) 68-pin PLCC (plastic leaded chip carrier)
b) 68-pin LCC (lead less chip carrier)
c) 68-pin PGA (pin grid array)
d) all of the mentioned

View Answer

Answer: d
Explanation: The 80286 is available in 68-pin PLCC (plastic leaded chip carrier), 68-pin LCC (lead less chip carrier) and 68-pin PGA (pin grid array) packages.




2 - Question

The clock frequency applied at the CLK pin is internally divided by
a) 2
b) 4
c) 8
d) 1

View Answer

Answer: a
Explanation: The clock frequency is divided by two internally, and is used for deriving fundamental timings for basic operations of the circuit.




3 - Question

The 8 address lines, A23-A16 of 80286 are zero during
a) memory transfer
b) address transfer
c) memory to processor transfer
d) I/O transfer

View Answer

Answer: d
Explanation: The address lines, A23-A16 are zero during I/O transfers.




4 - Question

The signals S1 (active low), S2 (active low) are
a) output signals
b) indicate initiation of bus cycle
c) define type of bus cycle with M/IO (active low)
d) all of the mentioned

View Answer

Answer: d
Explanation: The signals S1 (active low), S2 (active low) are active low status output signals, which indicate initiation of a bus cycle, and with M/IO (active low) and COD/INTA (active low), they define the type of the bus cycle.




5 - Question

If M/IO (active low) signal is ‘0’ then it indicates
a) I/O cycle
b) Memory cycle
c) I/O cycle or INTA cycle
d) I/O cycle or HALT cycle

View Answer

Answer: c
Explanation: If M/IO (active low) signal is ‘0’ then it indicates that an I/O cycle or INTA cycle is in the process, and if it is ‘1’, it indicates that a memory or a HALT cycle is in progress.




6 - Question

The LOCK (active low) is activated automatically by hardware using
a) XCHG signal
b) Interrupt acknowledge
c) Descriptor table access
d) All of the mentioned

View Answer

Answer: d
Explanation: The lock pin is used to prevent the other masters from gaining the control of the bus, for the current and the following bus cycles. This pin is activated by a “LOCK” instruction prefix, or automatically by hardware during XCHG, interrupt acknowledge or descriptor table access.




7 - Question

The pin that is used to insert wait states in a bus cycle is
a) WAIT
b) BHE (active low)
c) READY (active low)
d) WAIT(active low)

View Answer

Answer: c
Explanation: The active low READY pin is used to insert wait states in a bus cycle, for interfacing low speed peripherals. This signal is neglected during HLDA cycle.




8 - Question

The minimum number of clock cycles required in an input pulse width of the RESET pin is
a) 4
b) 2
c) 8
d) 16

View Answer

Answer: d
Explanation: The active high RESET input clears the internal logic of 80286, and re-initializes it. The reset input pulse width should be at least 16 clock cycles.




9 - Question

To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
a) CAP and ground
b) Output pin and ground
c) CAP and Vcc
d) NMI and ground

View Answer
Answer: a
Explanation: A 0.047microfarads, 12V capacitor is connected between the CAP pin and ground, to filter the output of the internal substrate bias generator.



10 - Question

The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions are
a) BUSY (active low)
b) PEACK (active low)
c) PEREQ
d) ERROR (active low)

View Answer

Answer: d
Explanation: An active ERROR (active low) signal causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions.

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