Engineering Questions with Answers - Multiple Choice Questions
MCQs on Rapid Execution Module, Memory Subsystem, Hyperthreading Technology
The units that are primarily used to resolve indirect mode of memory addressing is called
c) ALU and AGU
Explanation: The AGUs(Address Generation Units) are primarily used to resolve indirect mode of memory addressing.
The AGUs work at a speed of
a) equal to that of processor
b) twice the processor
c) thrice the processor
Explanation: The AGUs run at twice the processor speed.
Pentium 4 consists of
a) 4 ALUs
b) 4 AGUs
c) 2 ALUs and 2 AGUs
d) 4 ALUs and 4 AGUs
Explanation: Pentium 4 consists of 2 ALUs and 2 AGUs.
The number of instructions that can be executed per clock cycle by the ALU or AGU is
Explanation: As the speed of the units, ALU and AGU are doubled, which means that twice the number of instructions being executed per clock cycle.
The paging mechanism of IA-32 architecture has an extension as
a) page memory extension
b) page size extension
c) page address extension and page size extension
d) page memory extension and page size extension
Explanation: IA-32 architecture’s paging mechanism includes an extension that support
1. Page address extension to address space greater than 4GB.
2. Page size extension to map linear address to physical address in 4MB.
The linear address space is mapped into the processors physical address space either directly or through paging by
a) flat memory model
b) segmented memory model
c) flat or segmented memory model
Explanation: With the flat or segmented memory model, linear address space is mapped into the processors physical address space either directly or through paging.
The features of thread in threading process is
a) threads can be bunched together
b) threads are simple and light weight
c) threads are independent
d) all of the mentioned
Explanation: Threads may be bunched together in a process. Threads are independent, simple in structure and are lightweight in the sense that they may enhance the speed of operation of an overall process.
The process in which multiple threads correspond to the tracking of each individual object is known as
a) multiple thread system
b) multi thread parallelism
c) thread level parallelism
d) multi level parallelism
Explanation: The mutiple threads correspond to the tracking of each individual object. This kind of parallelism is known as thread level parallelism(TLP).
Which of the following is not a type of context switching?
a) time-slice multithreading
b) on chip multiprocessing
Explanation: A single processor can execute multiple threads by switching between them. The scheme of context switching may be several types. They are
1. Time-slice multithreading
2. On chip multiprocessing
The thread level parallelism is a process of
a) saving the context of currently executing process
b) flushing the CPU of the same process
c) loading the context of new next process
d) all of the mentioned
Explanation: The thread level parallelism is a process of
1. Saving the context of currently executing process.
2. Flushing the CPU of the same process.
3. Loading the context of new next process is called a context switch.