Engineering Questions with Answers - Multiple Choice Questions

MCQs on Priority of Bus Use By 80286, Bus Hold and HLDA Sequence, Interrupt Acknowledge Sequence

1 - Question

Which of the following is the highest priority usage among them?
a) second transfer cycle of a processor extension data transfer
b) third transfer cycle of a processor extension data transfer
c) hold request
d) second byte transfer of 2-byte transfer at an odd address

View Answer

Answer: d
Explanation: The second byte transfer of 2-byte transfer at an odd address, is the highest priority usage among the given usages.




2 - Question

The highest priority usage than any other usage is
a) transfer with LOCK (active low) signal
b) hold request
c) processor extension data transfer
d) data transfer performed by EU (execution unit)

View Answer

Answer: a
Explanation: The transfer with LOCK (active low) signal is the highest priority usage than any other usage.




3 - Question

The lowest priority usage among the following is
a) hold request
b) processor extension data transfer
c) prefetch operation to fetch and arrange next instruction bytes in queue
d) data transfer performed by EU for instruction execution

View Answer

Answer: c
Explanation: The order of priority usages, starting from the highest one to the lowest one, is given as
1. transfer with LOCK (active low) signal
2. second byte transfer of 2-byte transfer at an odd address
3. second or third transfer cycle of a processor extension data transfer
4. HOLD request
5. processor extension data transfer
6. data transfer performed by EU (execution unit)
7. prefetch operation to fetch and arrange next instruction bytes in queue.




4 - Question

As a response to the valid bus hold request, the bus is pushed into
a) TH (hold) state
b) Ts (status) state
c) Tc (command) state
d) Ti (idle) state

View Answer

Answer: a
Explanation: 80286 local bus is relinquished for another bus master if a valid bus hold request is received at the HOLD input pin. As a response to a valid bus hold request, the bus is pushed into TH state.




5 - Question

The bus arbiter relinquishes
a) Address
b) M/IO (active low)
c) COD/INTA (active low)
d) All of the mentioned

View Answer

Answer: d
Explanation: The address, M/IO (active low) and COD/INTA (active low) are relinquished by bus arbiter.




6 - Question

A valid HOLD request is ascertained only after the completion of
a) 34 clockcycles
b) 24 clockcycles and 80286 is SET
c) 34 clockcycles and 80286 is SET
d) 34 clockcycles and 80286 is RESET

View Answer

Answer: d
Explanation: Only after 34 clockcycles, after the 80286 is reset, a valid HOLD request should be ascertained.




7 - Question

The master PIC 8259A decides which of its slave interrupt controllers is to return the vector address, as a response of
a) first INTA (active low) pulse from 80286
b) second INTA (active low) pulse from 80286
c) third INTA (active low) pulse from 80286
d) none of the mentioned

View Answer

Answer: a
Explanation: In response to the first INTA (active low) pulse from 80286, the master PIC 8259A decides, which of its slave interrupt controllers is to return the vector address.




8 - Question

The slave (which is selected) sends the vector on data bus after the
a) first INTA (active low) pulse from 80286
b) second INTA (active low) pulse from 80286
c) third INTA (active low) pulse from 80286
d) none of the mentioned

View Answer

Answer: b
Explanation: The interrupt acknowledge sequence consists of two INTA (active low) pulses. After the second pulse, the selected slave sends the vector on D0-D7 data lines, and 80286 reads it.




9 - Question

The signal of 82C288, that enables the cascade address drivers, during INTA cycles is
a) DEN
b) DT/R (active low)
c) MCE
d) MB

View Answer

Answer: c
Explanation: The MCE (Master Cascade Enable) signal of 82C288 enables the cascade address drivers during INTA cycles, to select the slave using the local address bus.




10 - Question

The LOCK (active low) signal is activated during
a) Ti of first INTA cycle
b) Ts of first INTA cycle
c) Th of second INTA cycle
d) Ts of second INTA cycle

View Answer

Answer: b
Explanation: The LOCK (active low) signal is activated during Ts of first INTA cycle.




11 - Question

The number of idle states (Ti), that is allowed between two INTA cycles, to meet the 8259A speed and cascade address output delay is
a) 1
b) 2
c) 3
d) 4

View Answer

Answer: c
Explanation: The 80286 allows three idle states (Ti) between the two INTA cycles, to meet the 8259A speed and cascade address output delay.

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