Engineering Questions with Answers - Multiple Choice Questions

MCQs on Numeric Coprocessor – 80486DX

1 - Question

The first processor with an inbuilt floating point unit is
a) 80386
b) 80486
c) 80286
d) 8086

View Answer

Answer: b
Explanation: The 32-bit CPU 80486 from Intel is the first processor with an inbuilt floating point unit. 80486DX is the first CPU with an on chip floating point unit.




2 - Question

Which of the following signal is handled by bus control and request sequencer?
a) ADS#
b) PWT
c) RDY#
d) All of the mentioned

View Answer

Answer: d
Explanation: The bus control and request sequencer handle the signals like ADS#, PWT, RDY#, W/R#, INTR, NMI, LOCK#, HOLD, HLDA, RESET and M/IO# which basically controls the bus access and operations.




3 - Question

The unit that subjects the processor operation to boundary scan tests is
a) parity generation and control unit
b) prefetcher unit
c) boundary scan and control unit
d) segmentation unit

View Answer

Answer: c
Explanation: The boundary scan and control unit subjects the processor operation to boundary scan tests to ensure the correct operation of various components of the mother board.




4 - Question

The management of the virtual memory of the system and adequate protection to data or codes in the physical memory is provided by
a) segmentation unit
b) paging unit
c) attribute PLA
d) all of the mentioned

View Answer

Answer: d
Explanation: The segmentation unit, paging unit, attribute PLA, descriptor registers, translation look aside buffer and limit work together to manage the virtual memory of the system and provide the adequate protection to the codes or data in the physical memory.




5 - Question

The flag that is added to 80486 in additional to the flags similar to 80386 is
a) alignment check flag
b) parity check flag
c) conditional flag
d) all of the mentioned

View Answer

Answer: a
Explanation: The register set of 80486 is similar to that of the 80386 but only a flag called as alignment check flag is added to the flag register of 80386 to obtain the flag register of 80486.




6 - Question

The major limitation of 80386-387 system is
a) low speed
b) 80386 sends data using an I/O handshake technique
c) 80386 returns to real mode by reset operation
d) none of the mentioned

View Answer

Answer: b
Explanation: The major limitation of 80386-387 system is that the 80386 sends instruction or data to 80387 using an I/O handshake technique. To perform this handshaking and to carry additional house keeping tasks, 80386 requires 15 clock cycles or more.




7 - Question

The datatype that the 80486 doesnot support is
a) Signed and unsigned
b) ASCII
c) Floating point
d) None

View Answer

Answer: d
Explanation: The datatypes that 80486 supports are
1. Signed
2. Unsigned
3. Floating point
4. BCD
5. String
6. ASCII.




8 - Question

In Little Endian data format, the data is stored as
a) MSB is stored at lower memory address and LSB at higher memory address
b) LSB is stored at lower memory address and MSB at higher memory address
c) MSB is stored at general purpose registers
d) LSB is stored at general purpose registers

View Answer

Answer: b
Explanation: In Little Endian data format, for a data of size bigger than 1 byte, the LSB is stored at lower memory address and MSB at higher memory address.




9 - Question

The on-chip cache is used for storing
a) addresses of data
b) opcodes and data
c) data and their addresses
d) opcodes and their addresses

View Answer

Answer: b
Explanation: The unique feature of 80486 that is not available in 80386 is that the on-chip is used for storing opcodes and data.




10 - Question

The on-chip cache is controlled by
a) Cache disable(CD)
b) No write through(NW)
c) Cache disable and No write through
d) None of the mentioned

View Answer

Answer: c
Explanation: Cache disable(CD) and No write through(NW) bits of control register CR0. To completely disable cache, the CD and NW bits must be 11.




11 - Question

The on-chip cache can be flushed using external hardware using
a) FLUSH pin
b) TERMINATE pin
c) FLOW pin
d) Pin FLUSH# or using software

View Answer

Answer: d
Explanation: The on-chip cache can be flushed using external hardware using pin FLUSH# or using the software. The flushing operation clears all the valid bits for all the cache lines.

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