Engineering Questions with Answers - Multiple Choice Questions
MCQs on Memory Systems –3
1 - Question
MCQs on Writing Scheme of Cache Memory
Which of the following is the biggest challenge in the cache memory design?
a) delay
b) size
c) coherency
d) memory access
View Answer
Explanation: The coherency is a major challenge in designing the cache memory. The cache has to be designed by solving the problem of data coherency while remaining hardware and software compatible.
2 - Question
What arises when a copy of data is held both in the cache and in the main memory?
a) stall data
b) stale data
c) stop data
d) wait for the state
View Answer
Explanation: The stale data arises when the copy is held both in the cache memory and in the main memory. If either copy is modified, the other data become stale and the system coherency can be destroyed.
3 - Question
In which writing scheme does all the data writes go through to main memory and update the system and cache?
a) write-through
b) write-back
c) write buffering
d) no caching of writing cycle
View Answer
Explanation: There are different writing scheme in the cache memory which increases the cache efficiency and one such is the write-through in which all the data go to the main memory and can update the system as well as the cache. advertisement
4 - Question
In which writing scheme does the cache is updated but the main memory is not updated?
a) write-through
b) write-back
c) no caching of writing cycle
d) write buffering
View Answer
Explanation: The cache write-back mechanism needs a bus snooping system for the coherency. In this write-back scheme, the cache is updated first and the main memory is not updated.
5 - Question
In which writing scheme does the cache is not updated?
a) write-through
b) write-back
c) write buffering
d) no caching of writing cycle
View Answer
Explanation: The no caching write cycle does not update the cache but the data is written to the cache. If the previous data had cached, that entry is invalid and will not use. This makes the processor fetch data directly from the main memory.
6 - Question
Which writing mechanism forms the backbone of the bus snooping mechanism?
a) write-back
b) write-through
c) no caching of write cycles
d) write buffer
View Answer
Explanation: The no caching of write cycle seems to be wasteful because it does not update the cache, and if any previous data is cached, that entry might be an error and is not used. So the processor access data from the main memory but this writing scheme forms the backbone of the bus snooping system for the coherency issue.
7 - Question
What is the main idea of the writing scheme in the cache memory?
a) debugging
b) accessing data
c) bus snooping
d) write-allocate
View Answer
Explanation: There are four main writing scheme in the cache memory which is, write-through, write-back, no caching of the write cycle and write buffer. All these writing schemes are designed for bus snooping which can reduce the coherency.
8 - Question
In which scheme does the data write via a buffer to the main memory?
a) write buffer
b) write-back
c) write-through
d) no caching of the write cycle
View Answer
Explanation: The write-buffer is slightly similar to the write-through mechanism in which data is written to the main memory but in write buffer mechanism data writes to the main memory via a buffer.
9 - Question
Which of the following can allocate entries in the cache for any data that is written out?
a) write-allocate cache
b) read-allocate cache
c) memory-allocate cache
d) write cache
View Answer
Explanation: A write-allocate cache allocates the entries in the cache for any data that is written out. If the data is transferred to the external memory so that, when it is accessed again, the data is already waiting in the cache. It works efficiently if the size of the cache is large and it does not overwrite even though it is advantageous.
10 - Question
Which of the following uses a bus snooping mechanism?
a) MC88100
b) 8086
c) 8051
d) 80286
View Answer
Explanation: The bus snooping mechanism uses a combination of cache tag status, write policies and bus monitoring to ensure coherency. MC88100 or MC88200 uses bus snooping mechanism.
11 - Question
What leads to the development of MESI and MEI protocol?
a) cache size
b) cache coherency
c) bus snooping
d) number of caches
View Answer
Explanation: The problem of cache coherency lead to the formation of two standard mechanisms called MESI and MEI protocol. MC88100 have MESI protocol and MC68040 uses an MEI protocol.
12 - Question
Which of the following is also known as Illinois protocol?
a) MESI protocol
b) MEI protocol
c) Bus snooping
d) Modified exclusive invalid
View Answer
Explanation: The MESI protocol is also known as Illinois protocol because of its formation at the University of Illinois.
13 - Question
What does MESI stand for?
a) modified exclusive stale invalid
b) modified exclusive shared invalid
c) modified exclusive system input
d) modifies embedded shared invalid
View Answer
Explanation: The MESI protocol supports a shared state which is a formal mechanism for controlling the cache coherency by using the bus snooping techniques. MESI refers to the states that cached data can access. In MESI protocol, multiple processors can cache shared data.
14 - Question
What does MEI stand for?
a) modified embedded invalid
b) modified embedded input
c) modified exclusive invalid
d) modified exclusive input
View Answer
Explanation: MEI protocol is less complex and is easy to implement. It does not allow shared state for the cache.
15 - Question
Which protocol does MPC601 use?
a) MESI protocol
b) MEI protocol
c) MOSI protocol
d) MESIF protocol
View Answer
Explanation: MPC601 uses a MESI protocol, that is they have a shared state for data accessing in the cache. It can reduce the cache coherency but the cache coherency is processor specific. So different processors have different cache coherency implementations.
16 - Question
MCQs on Burst Interfaces
Which of the following include special address generation and data latches?
a) burst interface
b) peripheral interface
c) dma
d) input-output interfacing
View Answer
Explanation: The burst interfacing has special memory interfaces which include special address generation and data latches that help in the high performance of the processors. It takes the advantages of both the nibble mode memories and paging.
17 - Question
Which of the following makes use of the burst fill technique?
a) burst interfaces
b) dma
c) peripheral interfaces
d) input-output interfaces
View Answer
Explanation: The burst interfaces use the burst fill technique in which the processor will access four words in succession, which fetches the complete cache line or written out to the memory.
18 - Question
How did burst interfaces access faster memory?
a) segmentation
b) dma
c) static column memory
d) memory
View Answer
Explanation: The speed of the memory can be improved by the page mode or the static column memory which offer a faster access in a single cycle. advertisement
19 - Question
Which of the following memory access can reduce the clock cycles?
a) bus interfacing
b) burst interfacing
c) dma
d) dram
View Answer
Explanation: The burst interfaces reduces the clock cycles. For fetching four words with a three clock memory, it will take 12 clock cycle but in the burst interface, it will only take five clocks to access the data.
20 - Question
How many clocks are required for the first access in the burst interface?
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: In the burst interface, the first access of the memory address requires two clock cycles and a single cycle for the remaining memory address.
21 - Question
In which of the following access, the address is supplied?
a) the first access
b) the second access
c) third access
d) fourth access
View Answer
Explanation: In the burst interface, the address is supplied only for the first access and not for the remaining accesses. An external logic is required for the additional addresses for the memory interface.
22 - Question
What type of timing is required for the burst interfaces?
a) synchronous
b) equal
c) unequal
d) symmetrical
View Answer
Explanation: The burst interfacing uses an unequal timing. It takes two clocks for the first access and only one for the remaining accesses which make it an unequal timing.
23 - Question
How can gate delays be reduced?
a) synchronous memory
b) asynchronous memory
c) pseudo asynchronous memory
d) symmetrical memory
View Answer
Explanation: The burst interfaced is associated with the SRAM and for the efficiency of the SRAM, it uses a synchronous memory on-chip latches to reduce the gate delays.
24 - Question
In which memory does the burst interfaces act as a part of the cache?
a) DRAM
b) ROM
c) SRAM
d) Flash memory
View Answer
Explanation: The burst interface is associated with the static RAM.
25 - Question
Which of the following uses a wrap around burst interfacing?
a) MC68030
b) MC68040
c) HyperBus
d) US 5729504 A
View Answer
Explanation: MC68040 is developed by the Motorola which uses a wrap around burst interfacing. MC68030 is also developed by Motorola but it uses a linear line fill burst. HyperBus can switch to both linear and wrap around burst. US 5729504 A uses a linear burst fill.
26 - Question
Which of the following is a Motorola’s protocol product?
a) MCM62940
b) Avalon
c) Slave interfaces
d) AXI slave interfaces
View Answer
Explanation: MCM62940 protocol is developed by Motorola, whereas Slave interfaces, AXI slave interfaces are for ARM. Avalon is developed by Altera.
27 - Question
Which of the following uses a linear line fill interfacing?
a) MC68040
b) MC68030
c) US 74707 B2
d) Hyper Bus
View Answer
Explanation: MC68030 uses a linear burst fill whereas MC68040, US 74707 B2 uses to wrap around burst interfacing. HyperBus can switch to both linear and wrap around interfacing.
28 - Question
Which of the following protocol matches the Intel 80486?
a) MCM62940
b) MCM62486
c) US 74707 B2
d) Hyper Bus
View Answer
Explanation: The MCM62486 has an on-chip counter that matches the Intel 80486 and is developed by the Motorola.
29 - Question
Which of the following protocol matches the MC68040?
a) MCM62486
b) US 5729504 A
c) HyperBus
d) MCM62940
View Answer
Explanation: The MCM62940 and MCM62486 are the specific protocols developed by Motorola, in which the MCM62940 has an on-chip counter which matches the wrap-around burst interfacing of the MC68040.
30 - Question
MCQs on Segmentation and Paging
The modified bit is also known as
a) dead bit
b) neat bit
c) dirty bit
d) invalid bit
View Answer
Explanation: The dirty bit is said to be set if the processor modifies its memory. This bit indicates that the associative set of blocks regarding the memory is modified and has not yet saved to the storage.
31 - Question
Which of the following have an 8 KB page?
a) DEC Alpha
b) ARM
c) VAX
d) PowerPC
View Answer
Explanation: DEC Alpha divides its memory into 8KB pages whereas VAX is a small page which is only 512 bytes in size. PowerPC pages are normally 4 KB and ARM is having 4 KB and 64 KB pages.
32 - Question
Which of the following address is seen by the memory unit?
a) logical address
b) physical address
c) virtual address
d) memory address
View Answer
Explanation: The logical address is the address generated by the CPU. It is also known as virtual address. The physical address is the address which is seen by the memory unit. advertisement Learn more
33 - Question
Which of the following modes offers segmentation in the memory?
a) virtual mode
b) real mode
c) protected mode
d) memory mode
View Answer
Explanation: The main memory can split into small blocks by the method of paging and segmentation and these mechanisms are possible only in protected mode.
34 - Question
Which of the following is necessary for the address translation in the protected mode?
a) descriptor
b) paging
c) segmentation
d) memory
View Answer
Explanation: The address translation from the logical address to physical address partitions the main memory into different blocks which is called segmentation. Each of these blocks have a descriptor which possesses a descriptor table. So the size of every block is very important for the descriptor.
35 - Question
What does “G” in the descriptor entry describe?
a) gain
b) granularity
c) gate voltage
d) global descriptor
View Answer
Explanation: The granularity bit controls the resolution of the segmented memory. When it is set to logic one, the resolution is 4 KB. When the granularity bit is set to logic zero, the resolution is 1 byte.
36 - Question
How many types of tables are used by the processor in the protected mode?
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: There are two types of descriptor table used by the processor in the protected mode which are GDT and LDT, that is global descriptor table and local descriptor table respectively.
37 - Question
What does the table indicator indicate when it is set to one?
a) GDT
b) LDT
c) remains unchanged
d) toggles with GTD and LTD
View Answer
Explanation: The table indicator is a part of selector that selects which table is to be used. If the table indicator is set to logic one, the will use the local descriptor table and if the table indicator is set to logic zero, it will use the global descriptor table.
38 - Question
What does GDTR stand for?
a) global descriptor table register
b) granularity descriptor table register
c) gate register
d) global direct table register
View Answer
Explanation: The global descriptor table register is a special register which have the linear address and the size of its own GDT. Both the global descriptor table register and local descriptor table register are located in the global descriptor table.
39 - Question
What does PMMU stands for?
a) protection mode memory management unit
b) paged memory management unit
c) physical memory management unit
d) paged multiple management unit
View Answer
Explanation: The paged memory management unit is used to decrease the amount of storage needed in the page tables, that is, a multi-level tree structure is used. MC68030, PowerPC, ARM 920 uses a paged memory management unit.
40 - Question
Which of the following support virtual memory?
a) segmentation
b) descriptor
c) selector
d) paging
View Answer
Explanation: The paging mechanism supports the virtual memory. Paging helps in creating virtual address space which has a major role in memory management.
41 - Question
What does DPL in the descriptor describes?
a) descriptor page level
b) descriptor privilege level
c) direct page level
d) direct page latch
View Answer
Explanation: The descriptor privilege level is used to restrict access to the segment which helps in protection mechanism. It acquires two bit of the descriptor.
42 - Question
What does “S” bit describe in a descriptor?
a) descriptor type
b) small type
c) page type
d) segmented type
View Answer
Explanation: The S bit determines whether it is a system segment or a normal segment. When the S bit is set, it might be a code segment or a data segment. If the S bit clears, it is a system segment.
43 - Question
MCQs on Memory Protection Unit
How many regions are created by the memory range in the ARM architecture?
a) 4
b) 8
c) 16
d) 32
View Answer
Explanation: The memory protection unit in the ARM architecture divides the memory into eight separate regions. Each region can be small as well as big ranging from 4 Kbytes to 4 Gbytes.
44 - Question
How many bits does the memory region in the ARM memory protection unit have?
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: The memory region possesses three bits which are the cacheable bit, bufferable bit and access permission bit.
45 - Question
Which of the following uses a priority level for permitting data?
a) ARM memory management unit
b) ARM protection memory management unit
c) Bus interface unit
d) Execution unit
View Answer
Explanation: In the ARM protection architecture, the memory is divided into some regions of size 4 Kbytes to 4 Gbytes. These regions possess bits called the cacheable bit, buffer bit, and access permitted bits. The regions are numbered as per priority level for which the permission bits takes the precedence if any of the regions gets overlapped. advertisement
46 - Question
What type of bit in the ARM memory mimics to that of the protection unit of ARM management unit?
a) permission bit
b) buffer bit
c) cacheable bit
d) access permission bit
View Answer
Explanation: The ARM architecture memory protection unit divides the memory range into different regions of size ranging from 4 Kbytes to 4 Gbytes. Each region is associated with certain bits called the cacheable bit, buffer bit, and access permitted bit. These bits are similar to the permission bit in the ARM memory management unit architecture which is stored in the control register.
47 - Question
Which of the following bits are used to control the cache behaviour?
a) cacheable bit
b) buffer bit
c) cacheable bit and buffer bit
d) cacheable bit, buffer bit and permission access bit
View Answer
Explanation: The cacheable bit and the buffer bit are used to control the behaviour of cache. Depending on the cacheable bit and the buffer bit, the memory access will complete successfully.
48 - Question
Which of the following unit provides security to the processor?
a) bus interface unit
b) execution unit
c) peripheral unit
d) memory protection unit
View Answer
Explanation: The memory management unit and the memory protection unit provides security to the processor by trapping the invalid memory accesses before they corrupt other data.
49 - Question
Which of the following includes a tripped down memory management unit?
a) memory protection unit
b) memory real mode
c) memory management unit
d) bus interface unit
View Answer
Explanation: The memory protection unit allows a tripped memory down memory management unit in which the memories are partitioned and protected without any address translation. This can remove the time consumption in the address translation thereby increases the speed.
50 - Question
Which of the following can reduce the chip size?
a) memory management unit
b) execution unit
c) memory protection unit
d) bus interface unit
View Answer
Explanation: The memory protection unit have many advantages over the other units. It can reduce the chip size, cost and power consumption.
51 - Question
How does the memory management unit provide the protection?
a) disables the address translation
b) enables the address translation
c) wait for the address translation
d) remains unchanged
View Answer
Explanation: The memory management unit can be used as a protection unit by disabling the address translation that is, the physical address and the logical address are the same.
52 - Question
Which of the following is used to start a supervisor level?
a) error signal
b) default signal
c) wait for the signal
d) interrupt signal
View Answer
Explanation: If memory access from the software does not access the correct data, an error signal is generated which will start a supervisor level software for the decision.
53 - Question
What happens when a task attempts to access memory outside its own address space?
a) paging fault
b) segmentation fault
c) wait
d) remains unchanged
View Answer
Explanation: Different tasks assign their own address space and whenever a task access memory outside its own address space, a segmentation fault result and which in turn results in the termination of the offending application.