Engineering Questions with Answers - Multiple Choice Questions

# MCQs on Memory Systems-2

1 - Question

MCQs on DRAM Refreshing Techniques
Which is the very basic technique of refreshing DRAM? a) refresh cycle b) burst refresh c) distributive refresh d) software refresh
View Answer Answer: a Explanation: The DRAM needs to be periodically refreshed and the very basic technique is a special refresh cycle, during these cycles no other access is permitted. The whole chip is refreshed within a particular time period otherwise, the data will be lost.

2 - Question

How is the refresh rate calculated? a) by refresh time b) by the refresh cycle c) by refresh cycle and refresh time d) refresh frequency and refresh cycle
View Answer Answer: c Explanation: The time required for refreshing the whole chip is known as refresh time. The number of access needed to complete refresh is called as the number of cycles. The number of cycles divided by the refresh time gives the refresh rate.

3 - Question

Which is the commonly used refresh rate? a) 125 microseconds b) 120 microseconds c) 130 microseconds d) 135 microseconds

4 - Question

How can we calculate the length of the refresh cycle? a) twice of normal access b) thrice of normal access c) five times of normal access d) six times of normal access
View Answer Answer: a Explanation: Each of the refresh cycles is approximately as twice as the length of the normal access, for example, a 70ns DRAM has a refresh cycle time of 130ns.

5 - Question

What type of error occurs in the refresh cycle of the DRAM? a) errors in data b) power loss c) timing issues d) not accessing data
View Answer Answer: c Explanation: When the refresh cycle in a DRAM is running, it will not access data, so the processor will have to wait for its data. This arises some timing issues.

6 - Question

What is the worst case delay of the burst refresh in 4M by 1 DRAM? a) 0.4ms b) 0.2ms c) 170ns d) 180ns
View Answer Answer: b Explanation: A 4M by 1 DRAM have 1024 refresh cycles. Bursting delay will be 0.2ms that are, the worst case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns.

7 - Question

Which refresh techniques depends on the size of time critical code for calculating the refresh cycle? a) burst refresh b) distributed refresh c) refresh cycle d) software refresh
View Answer Answer: b Explanation: Most of the system uses the distributed method and depending on the size of the time critical code, the number of refresh cycles can be calculated.

8 - Question

Which of the following uses a timer for refresh technique? a) RAS b) CBR c) software refresh d) CAS
View Answer Answer: c Explanation: The software refresh performs the action by using a routine to periodically cycle through the memory and refreshes. It uses a timer in the program generating an interrupt. This interrupt performs the refreshing part in the DRAM.

9 - Question

What is the main disadvantage in the software refresh of the DRAM? a) timer b) delay c) programming delay d) debugging
View Answer Answer: d Explanation: Debugging in software refresh is very difficult to perform because they may stop the refreshing and if the refreshing is stopped, the contents get lost.

10 - Question

Which refresh technique is useful for low power consumption? a) Software refresh b) CBR c) RAS d) Burst refresh
View Answer Answer: b Explanation: CBR that is, CAS before RAS refresh is the one which is commonly used. It has low power consumption quality because it does not have address bus and the buffers can be switched off. It is worked by using an internal address counter which is stored on the memory chip itself and this can be incremented periodically.

11 - Question

Which refreshing techniques generate a recycled address? a) RAS b) CBR c) Distributed refresh d) Software refresh

12 - Question

Which of the following uses a software refresh in the DRAM? a) 8086 b) 80386 c) Pentium d) Apple II personal computer
View Answer Answer: d Explanation: The Apple II personal computer has a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.

13 - Question

How do CBR works? a) by asserting CAS before RAS b) by asserting CAS after RAS c) by asserting RAS before CAS d) by asserting CAS only
View Answer Answer: a Explanation: CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.

14 - Question

Which of the refresh circuit is similar to CBR? a) software refresh b) hidden refresh c) burst refresh d) distribute refresh
View Answer Answer: b Explanation: In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. At the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of the RAS signal at the end of the read cycle starts a CBR refresh cycle.

15 - Question

Which technology is standardized in DRAM for determining the maximum time interval between the refresh cycle? a) IEEE b) RAPID c) JEDEC d) UNESCO
View Answer Answer: c Explanation: The maximum time interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification.

16 - Question

MCQs on DRAM Interfaces
In which pin does the data appear in the basic DRAM interfacing?
a) dout pin
b) din pin
c) clock
d) interrupt pin
Explanation: In the basic DRAM interfacing, the higher order bits asserts the RAS signal and the lower order bits asserts the CAS signal. When the access got expired, the data appears on the dout pin and is latched by the processor.

17 - Question

What is the duration for memory refresh to remain compatible?
a) 20 microseconds
b) 12 microseconds
c) 15 microseconds
d) 10 microseconds
Explanation: The memory refresh is performed every 15 microseconds in order to remain compatible.

18 - Question

Which interfacing method lowers the speed of the processor?
a) basic DRAM interface
b) page mode interface
c) page interleaving
d) burst mode interface
Explanation: The direct method access limits the wait state-free operation which lowers the processor speed. advertisement

19 - Question

What is EDO RAM?
a) extreme data operation
b) extended direct operation
c) extended data out
d) extended DRAM out
Explanation: EDO RAM is a special kind of random access memory which can improve the time to read from the memory on faster microprocessors. The example of such a microprocessor is Intel Pentium.

20 - Question

What is RDRAM?
a) refresh DRAM
b) recycle DRAM
c) Rambus DRAM
d) refreshing DRAM
Explanation: Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.

21 - Question

Which of the following can transfer up to 1.6 billion bytes per second?
a) DRAM
b) RDRAM
c) EDO RAM
d) SDRAM
Explanation: The Rambus RAM can transfer up to 1.6 billion bytes per second. It possesses RAM controller, a bus which connects the microprocessor and the device, and random access memory.

22 - Question

Which of the following cycle is larger than the access time?
a) write cycle
b) set up time
d) hold time
Explanation: The read cycle in the DRAM interfacing is larger than the access time because of the precharge time.

23 - Question

Which mode of operation selects an internal page of memory in the DRAM interfacing?
a) page interleaving
b) page mode
c) burst mode
d) EDO RAM
Explanation: In the page mode operation, the row address is provided as normal but the RAS signal is left asserted. This, in turn, selects an internal page within the DRAM memory where any bit of data can be accessed by placing the column address and asserting CAS.

24 - Question

What is the maximum time that the RAS signal can be asserted in the page mode operation?
a) 5 microseconds
b) 10 microseconds
c) 15 microseconds
d) 20 microseconds
Explanation: The maximum time that the RAS signal can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.

25 - Question

Which of the following mode of operation in the DRAM interfacing has a page boundary?
a) burst mode
b) EDO RAM
c) page mode
d) page interleaving
Explanation: The page mode operation have memory cycles that exhibit some form of locality, that is, stay within the page boundary which causes page missing when there is access outside the page boundary and two or more wait states.

26 - Question

Which mode offers the banking of memory in the DRAM interfacing technique?
a) page mode
b) basic DRAM interfacing
c) page interleaving
d) burst mode
Explanation: The accessing of data outside the page boundary can cause missing of pages in the page mode operation. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such mode is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.

27 - Question

Which of the following has a fast page mode RAM?
a) burst mode
b) page interleaving
c) EDO memory
d) page mode
Explanation: Extended data out memory is a fast page mode RAM which has a faster cycling process which makes EDO memory a faster page mode access.

28 - Question

Which mode reduces the need for fast static RAMs?
a) page mode
b) page interleaving
c) burst mode
d) EDO memory
Explanation: The page mode, nibble mode devices can provide data fastly when the new column address is given. In burst mode operation, the processor can fetch more data than it needs and keeps the remaining data in an internal cache for the future use which can reduce the need for fast static RAMs.

29 - Question

Which of the following is also known as hyper page mode enabled DRAM?
a) page mode
b) EDO DRAM
c) burst EDO DRAM
d) page interleaving
Explanation: The EDO DRAM is also known as hyper page mode enable DRAM because of the faster page mode operation along with some additional features.

30 - Question

What does BEDO DRAM stand for?
a) burst EDO DRAM
b) buffer EDO DRAM
c) BIBO EDO DRAM
d) bilateral EDO DRAM
Explanation: The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory addresses in one burst. It also supports pipeline stages which allow the page access cycle into two parts.

31 - Question

MCQs on Cache Memory
Which of the following is more quickly accessed?
a) RAM
b) Cache memory
c) DRAM
d) SRAM
Explanation: The cache memory is a small random access memory which is faster than a normal RAM. It has a direct connection with the CPU otherwise, there will be a separate bus for accessing data. The processor will check whether the copy of the required data is present in the cache memory if so it will access the data from the cache memory.

32 - Question

Which factor determines the effectiveness of the cache?
a) hit rate
b) refresh cycle
c) refresh rate
d) refresh time
Explanation: The proportion of accesses of data that forms the cache hit, which measures the effectiveness of the cache memory.

33 - Question

Which of the following determines a high hit rate of the cache memory?
a) size of the cache
b) number of caches
c) size of the RAM
d) cache access
Explanation: The size of the cache increases, a large amount of data can be stored, which can access more data which in turn increases the hit rate of the cache memory. advertisement

34 - Question

Which of the following is a common cache?
a) DIMM
b) SIMM
c) TLB
d) Cache
Explanation: The translation lookaside buffer is common cache memory seen in almost all CPUs and desktops which are a part of the memory management unit. It can improve the virtual address translation speed.

35 - Question

Which factor determines the number of cache entries?
a) set commutativity
b) set associativity
c) size of the cache
d) number of caches
Explanation: The set associativity is a criterion which describes the number of cache entries which could possibly contain the required data.

36 - Question

What is the size of the cache for an 8086 processor?
a) 64 Kb
b) 128 Kb
c) 32 Kb
d) 16 Kb
Explanation: The 8086 processor have a 64 Kbytes cache, beyond this size, the cost will be extremely high.

37 - Question

How many possibilities of mapping does a direct mapped cache have?
a) 1
b) 2
c) 3
d) 4
Explanation: The direct mapped cache only have one possibility to fetch data whereas a two-way system, there are two possibilities, for a three-way system, there are three possibilities and so on. It is also known as the one-way set associative cache.

38 - Question

Which of the following allows speculative execution?
a) 12-way set associative cache
b) 8-way set associative cache
c) direct mapped cache
d) 4-way set associative cache
Explanation: The direct mapped cache has the advantage of allowing a simple and fast speculative execution.

39 - Question

Which of the following refers to the number of consecutive bytes which are associated with each cache entry?
a) cache size
b) associative set
c) cache line
d) cache word
Explanation: The cache line refers to the number of consecutive bytes which are associated with each cache entry. The data is transferred between the memory and the cache in a particular size which is called a cache line.

40 - Question

Which factor determines the cache performance?
a) software
b) peripheral
c) input
d) output
Explanation: The cache performance is completely dependent on the system and software. In software, the processor checks out each loop and if a duplicate is found in the cache memory, immediately it is accessed.

41 - Question

What are the basic elements required for cache operation?
a) memory array, multivibrator, counter
b) memory array, comparator, counter
c) memory array, trigger circuit, a comparator
d) memory array, comparator, CPU
Explanation: The cache memory operation is based on the address tag, that is, the processor generates the address which is provided to the cache and this cache stores its data with an address tag. The tag is compared with the address, if they did not match, the next tag is checked. If they match, a cache hit occurs, the data is passed to the processor. So the basic elements required is a memory array, comparator, and a counter.

42 - Question

How many divisions are possible in the cache memory based on the tag or index address?
a) 3
b) 2
c) 4
d) 5
Explanation: There is four classification based on the tag or index address corresponds to a virtual or physical address. They are PIPT, VIVT, PIVT, VIPT that is, physically indexed physically tagged, virtually indexed virtually tagged, physically indexed virtually tagged, virtually indexed physically tagged respectively.

43 - Question

What does DMA stand for?
a) direct memory access
b) direct main access
c) data main access
Explanation: The DMA is direct memory access which can modify the memory without the help of the processor. If any kind of memory access by DMA to be done, it will passes a request to the processor bus and the processor provides an acknowledgment and gives the control of the bus to the DMA.

44 - Question

MCQs on Size of Cache
Which of the following cache has a separate comparator for each entry?
a) direct mapped cache
b) fully associative cache
c) 2-way associative cache
d) 16-way associative cache
Explanation: A fully associative cache have a comparator for each entry so that all the entries can be tested simultaneously.

45 - Question

What is the disadvantage of a fully associative cache?
a) hardware
b) software
c) memory
d) peripherals
Explanation: The major disadvantage of the fully associative cache is the amount of hardware needed for the comparison increases in proportion to the cache size and hence, limits the fully associative cache.

46 - Question

How many comparators present in the direct mapping cache?
a) 3
b) 2
c) 1
d) 4
Explanation: The direct mapping cache have only one comparator so that only one location possibly have all the data irrespective of the cache size. advertisement

47 - Question

Which mapping of cache is inefficient in software viewpoint?
a) fully associative
b) 2 way associative
c) 16 way associative
d) direct mapping
Explanation: The direct mapping cache organization is simple from the hardware design aspects but it is inefficient in the software viewpoint.

48 - Question

Which mechanism splits the external memory storage into memory pages?
a) index mechanism
b) burst mode
c) distributive mode
d) a software mechanism
Explanation: The index mechanism splits the external memory storage into a series of memory pages in which each page is the same size as the cache. Each page is mapped to the cache so that each page can have its own location in the cache.

49 - Question

Which of the following cache mapping can prevent bus thrashing?
a) fully associative
b) direct mapping
c) n way set associative
d) 2 way associative
Explanation: Only one data can be accessed in direct mapping that is, if one word is accessed at a time, all other words are discarded at the same time. This is known as bus thrashing which can be solved by splitting up the caches so there are 2,4,..n possible entries available. The major advantage of the set associative cache is its capability to prevent the bus thrashing at the expense of hardware.

50 - Question

Which cache mapping have a sequential execution?
a) direct mapping
b) fully associative
c) n way set associative
d) burst fill
Explanation: The burst fill mode of cache mapping have a sequential nature of executing instructions and data access. The instruction fetches and execution accesses to sequential memory locations until it has a jump instruction or a branch instruction. This kind of cache mapping is seen in the MC68030 processor.

51 - Question

Which address is used for a tag?
Explanation: The cache memory uses either a physical address or logical address for its tag data. For a logical cache, the tag refers to a logical address and for a physical cache, the tag refers to the physical address.

52 - Question

In which of the following the data is preserved within the cache?
a) logical cache
b) physical cache
c) unified cache
d) harvard cache
Explanation: In the physical cache, the data is preserved within the cache because it does not flush out during the context switching but on the other hand, the logical cache flushes out the data and clear it during a context switching.

53 - Question

a) debugging
b) delay
c) data preservation
d) data cleared
Explanation: The physical address access the data through the memory management unit which causes a delay.

54 - Question

Which cache memory solve the cache coherency problem?
a) physical cache
b) logical cache
c) unified cache
d) harvard cache
Explanation: The physical cache is more efficient and can provide the cache coherency problem solved and MMU delay is kept to a minimum. PowerPC is an example for this advantage.

55 - Question

What type of cache is used in the Intel 80486DX?
a) logical
b) physical
c) harvard
d) unified
Explanation: The Intel 80486DX processor has a unified cache. Similarly, Motorola MPC601PC also uses the unified cache. The unified cache has the same mechanism to store both data and instructions.

56 - Question

Which of the following has a separate cache for the data and instructions?
a) unified
b) harvard
c) logical
d) physical
Explanation: The Harvard cache have a separate cache for the data and the instruction whereas the unified cache has a same cache for the data and instructions.

57 - Question

Which type of cache is used the SPARC architecture?
a) unified
b) harvard
c) logical
d) physical
Explanation: The SPARC architecture uses logical cache whereas most of the internal cache designed now, uses physical cache because data is not flushed out in this cache.

58 - Question

Which of the following approach uses more silicon area?
a) unified
b) harvard
c) logical
d) physical