Engineering Questions with Answers - Multiple Choice Questions

MCQs on Interrupts and Exceptions

1 - Question

MCQs on Introduction of Interrupts
The time taken to respond to an interrupt is known as
a) interrupt delay
b) interrupt time
c) interrupt latency
d) interrupt function
View Answer Answer: c
Explanation: The interrupts are the most important function of the embedded system and are responsible for many problems while debugging the system. The time taken to respond to an interrupt is called the interrupt latency.



2 - Question

Into how many parts does the interrupt can split the software?
a) 2
b) 3
c) 4
d) 5
View Answer Answer: a
Explanation: The software interrupt can split into two parts. These are foreground work and background work.



3 - Question

Which of the following allows the splitting of the software?
a) wait statement
b) ready
c) interrupt
d) acknowledgement
View Answer Answer: c
Explanation: The interrupt can make the software into two main parts and these are foreground work and background work. advertisement



4 - Question

Which part of the software is transparent to the interrupt mechanism?
a) background
b) foreground
c) both background and foreground
d) lateral ground
View Answer Answer: a
Explanation: The interrupt mechanism is transparent to the background software, that is, the background software is not aware of the existence of the foreground software.



5 - Question

Which part of the software performs tasks in response to the interrupts?
a) background
b) foreground
c) lateral ground
d) both foreground and background
View Answer Answer: b
Explanation: In the foreground work, the tasks are performed in response to the interrupts but in the background work, the tasks are performed while waiting for an interrupt.



6 - Question

In which of the following method does the code is written in a straight sequence?
a) method 1
b) timing method
c) sequence method
d) spaghetti method
View Answer Answer: d
Explanation: In the spaghetti method, the code is written in a straight sequence in which the analysis software goes and polls the port to see if there is data.



7 - Question

Which factor depends on the number of times of polling the port while executing the task?
a) data
b) data transfer rate
c) data size
d) number of bits
View Answer Answer: b
Explanation: The data transfer rate can determine the number of times the port is polled while executing the task.



8 - Question

Which of the following can improve the quality and the structure of a code?
a) polling
b) subroutine
c) sequential code
d) concurrent code
View Answer Answer: b
Explanation: The subroutine can improve the quality and the structure of the code. By using the polling method, as the complexity increases the software structure rapidly fall and it will become inefficient. So the subroutine method is adopted.



9 - Question

Which of the following are asynchronous to the operation?
a) interrupts
b) software
c) DMA
d) memory
View Answer Answer: a
Explanation: The interrupts are asynchronous to the operation and therefore can be used with systems that are the event as opposed to the time driven.



10 - Question

Which of the following can be used to create time-driven systems?
a) memory
b) input
c) output
d) interrupts
View Answer Answer: d
Explanation: The interrupts which are asynchronous can be used with systems that are the event as opposed to the time driven.



11 - Question

What does ISR stand for?
a) interrupt standard routine
b) interrupt service routine
c) interrupt software routine
d) interrupt synchronous routine
View Answer Answer: b
Explanation: The data transfer codes are written as part of the interrupt service routine which is associated with the interrupt generation by the hardware.



12 - Question

Which can activate the ISR?
a) interrupt
b) function
c) procedure
d) structure
View Answer Answer: a
Explanation: When the port receives the data, it will generate an interrupt which in turn activates the ISR.



13 - Question

Which code is written as part of the ISR?
a) data receive code
b) sequential code
c) data transfer code
d) concurrent code
View Answer Answer: c
Explanation: The data transfer codes are written as part of the interrupt service routine which is associated with the interrupt generation by the hardware.



14 - Question

MCQs on Sources of Interrupts
Which interrupts are generated by the on-chip peripherals? a) internal b) external c) software d) hardware
View Answer Answer: a Explanation: The internal interrupts are generated by the serial and parallel ports which are on-chip peripherals.



15 - Question

Which of the following is the common method for connecting the peripheral to the processor? a) internal interrupts b) external interrupts c) software d) exception
View Answer Answer: b Explanation: The common method for connecting the peripheral to the processor is the external interrupts. The external interrupts are provided through the external pins which are connected to the peripherals.



16 - Question

Which interrupt can make a change in the processor’s mode? a) internal interrupt b) external interrupts c) exceptions d) software mode
View Answer Answer: c Explanation: An exception is an event which changes the software flow to process the event. It includes both internal and external interrupts which cause the processor to change to a service routine.



17 - Question

How many exceptions does an MC68000 have? a) 256 b) 128 c) 90 d) 70
View Answer Answer: c Explanation: The MC68000 have 256 table entries which describe 90 exceptions. advertisement



18 - Question

Which interrupts allows a protected state? a) internal interrupt b) external interrupt c) software interrupt d) both internal and external interrupts
View Answer Answer: c Explanation: The software interrupt can change the processor into a protected state by changing the program flow.



19 - Question

How a software interrupt is created? a) instruction set b) sequential code c) concurrent code d) porting
View Answer Answer: a Explanation: The software interrupts includes a set of instructions for handling interrupts. The instruction set allows a currently executing program to change its flow.



20 - Question

What does SWI stand for? a) standard interrupt instruction b) sequential interrupt instruction c) software interrupt instruction d) system interrupt instruction
View Answer Answer: c Explanation: The instruction set of software interrupts are provided by the special instruction set. One such is the SWI which is commonly used in Z80.



21 - Question

Which of the following use SWI as interrupt mechanism? a) PowerPC b) MC68000 c) Z80 d) IBM PC
View Answer Answer: c Explanation: The PowerPC and MC68000 use TRAP instruction set for accessing software interrupt. IBM PC uses 8086 NMI. Z80 uses SWI for accessing software interrupts.



22 - Question

Which of the following supplies additional data to the software interrupt? a) internal interrupt b) external interrupt c) software interrupt d) nmi
View Answer Answer: c Explanation: For using the software interrupt more effectively, the additional data are used, which specifies the type of the request and data parameters are passed to the specific ISR. This additional data are offered by certain registers.



23 - Question

Which software interrupt is used in MC68000? a) Internal interrupt b) TRAP c) SWI d) NMI
View Answer Answer: b Explanation: The MC68000 uses a software interrupt mechanism for accessing interrupts from the peripheral in which the instruction are created using the TRAP mechanism.



24 - Question

Which of the following are accessible by the ISR in software interrupt mechanism? a) register b) interrupt c) nmi d) memory
View Answer Answer: a Explanation: The additional data are offered by certain registers and these additional data are used to specify the type of the data parameter and the request with the specific ISR when running in the software interrupt mode.



25 - Question

What allows the data protection in the software interrupt mechanism? a) Different mode b) Same mode c) SWI d) TRAP
View Answer Answer: a Explanation: The switching between user mode and supervisor mode provides protection for the processor, that is, the different modes in the software interrupt allows the memory and the associated code and data to be protected from each other.



26 - Question

What does NMI stand for? a) non-machine interrupt b) non-maskable interrupt c) non-massive interrupt d) non-memory interrupt
View Answer Answer: b Explanation: The NMI stand for the non-maskable interrupt in which the external interrupts cannot be masked out.



27 - Question

Which NMI is used in the IBM PC? a) SWI b) TRAP c) 80×86 NMI d) Maskable interrupt
View Answer Answer: c Explanation: The most commonly used non-maskable interrupt is the 80×86 NMI, which is implemented in the IBM PC.



28 - Question

Which can be used to pass the status information to the calling software in the software interrupt mechanism? a) register b) memory c) flag d) nmi
View Answer Answer: a Explanation: In order to use the software interrupt more effectively, the additional data are used to specify the type of the request and data parameters are passed to the specific ISR. This additional data are offered by certain registers. These registers are accessible by the ISR and it can also be used to pass the status information back to the calling software.



29 - Question

MCQs on The mechanism of Interrupts
Which of the following uses clock edge to generate an interrupt?
a) edge triggered
b) level-triggered
c) software interrupt
d) nmi
View Answer Answer: a
Explanation: In the edge-triggered interrupt, the clock edge is used to generate an interrupt. The transition is from a logical low to high or vice versa.



30 - Question

In which interrupt, the trigger is dependent on the logic level?
a) edge triggered
b) level-triggered
c) software interrupt
d) nmi
View Answer Answer: b
Explanation: In the level-triggered interrupt, the trigger is completely dependent on the logic level. The processors may require the level to be in a certain clock width so that the shorter pulses which are shorter than the minimum pulse width are ignored.



31 - Question

At which point the processor will start to internally process the interrupt?
a) interrupt pointer
b) instruction pointer
c) instruction boundary
d) interrupt boundary
View Answer Answer: c
Explanation: After the recognition of the interrupt, and finds that it is not an error condition with the currently executing interrupt, then the interrupt will not be internally executed until the current execution has completed. This point is known as the instruction boundary. At this point, the processor will start to internally process the interrupt.



32 - Question

What does 80×86 use to hold essential data?
a) stack frame
b) register
c) internal register
d) flag register
View Answer Answer: a
Explanation: The MC68000 and 80×86 family use stack frame for holding the data whereas RISC processors use special internal registers. advertisement



33 - Question

What does the RISC processor use to hold the data?
a) flag register
b) accumulator
c) internal register
d) stack register
View Answer Answer: c
Explanation: The RISC processors uses special internal registers to hold data whereas the 80×86 and MC68000 family uses stack register to hold the data.



34 - Question

Which of the following is a stack-based processor?
a) MC68000
b) PowerPC
c) ARM
d) DEC Alpha
View Answer Answer: a
Explanation: The MC68000, Intel 80×86 and most of the b-bit controllers are based on the stack-based processors whereas PowerPC, DEC alpha, and ARM are RISC families which have a special internal register for holding the data.



35 - Question

Which of the following is used to reduce the external memory cycle?
a) internal hardware stack
b) internal software stack
c) external software stack
d) internal register
View Answer Answer: a
Explanation: Some of the processors use internal hardware stack which helps in reducing the external memory cycle necessary to store the stack frame.



36 - Question

How many interrupt levels are supported in the MC68000?
a) 2
b) 3
c) 4
d) 7
View Answer Answer: d
Explanation: The MC68000 has an external stack for holding the data. The MC68000 family supports a seven interrupt level which are encoded into three interrupt pins.



37 - Question

How many interrupt pins are used in MC68000?
a) 2
b) 3
c) 4
d) 5
View Answer Answer: b
Explanation: The MC68000 family supports a seven interrupt level which are encoded into three interrupt pins. These interrupt pins are IP0, IP1, and IP2.



38 - Question

Which priority encoder is used in MC68000?
a) 4-to-2 priority encoder
b) LS148 7-to-3
c) 2-to-4 priority encoder
d) LS148 3-to-7
View Answer Answer: b
Explanation: The LS148 7-to-3 priority encoder is used in MC68000. This converts the seven external pins into a three-bit binary code.



39 - Question

Which of the following converts the seven external pins into a 3-bit binary code?
a) priority encoder
b) 4-to-2 priority encoder
c) LS148 7-to-3
d) 2-to-4 priority encoder
View Answer Answer: c
Explanation: The LS148 7-to-3 priority encoder can convert the seven external pins into a three-bit binary code.



40 - Question

Which of the following ensures the recognition of the interrupt?
a) interrupt ready
b) interrupt acknowledge
c) interrupt terminal
d) interrupt start
View Answer Answer: b
Explanation: The interrupt level remains asserted until its interrupt acknowledgment cycle ensures the recognition of the interrupt.



41 - Question

Which of the following is raised to the interrupt level to prevent the multiple interrupt request?
a) internal interrupt mask
b) external interrupt mask
c) non-maskable interrupt
d) software interrupt
View Answer Answer: a
Explanation: The internal interrupt mask is raised to the interrupt level, in order to prevent the multiple interrupt acknowledgments.



42 - Question

MCQs on RISC Exceptions-I
What does MSR stand for? a) machine state register b) machine software register c) minimum state register d) maximum state register
View Answer Answer: a Explanation: The MSR is a machine state register. When the exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers while handling an exception.



43 - Question

How many supervisor registers are associated with the exception mode? a) 2 b) 3 c) 4 d) 5
View Answer Answer: a Explanation: When the exception is recognised, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.



44 - Question

What happens when an exception is completed? a) TRAP instruction executes b) SWI instruction executes c) RFI instruction executes d) terminal count increases
View Answer Answer: c Explanation: When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the processor moves to the supervisor mode and starts to execute the handler which is associated with the vector table. The handler examines the DSISR and FPSCR registers and carries out the required function. When it gets completed the RFI or return-from-interrupt instruction is executed. advertisement



45 - Question

How many general types of exceptions are there? a) 2 b) 3 c) 6 d) 4
View Answer Answer: d Explanation: There are four general types of exceptions. They are synchronous precise, asynchronous precise, synchronous imprecise and asynchronous imprecise.



46 - Question

In which of the exceptions does the external event causes the exception? a) synchronous exception b) asynchronous exception c) precise d) imprecise
View Answer Answer: b Explanation: The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.



47 - Question

Which of the exceptions are usually a catastrophic failure? a) imprecise exception b) precise exception c) synchronous exception d) asynchronous exception
View Answer Answer: a Explanation: An imprecise exception is a catastrophic failure in which the processor cannot continue processing or allow a particular task or program to continue.



48 - Question

Which of the exceptions allows the system reset or memory fault? a) imprecise exception b) precise exception c) synchronous exception d) asynchronous exception
View Answer Answer: a Explanation: The system reset or memory fault falls into the category of imprecise exceptions while accessing the vector table.



49 - Question

Which registers are used to determine the completion status? a) MSR b) flag register c) DSISR d) index register
View Answer Answer: c Explanation: The completion status can be determined by the information bits in the DSISR and FPSCR registers.



50 - Question

Which of the following does not support PowerPC architecture? a) synchronous precise b) asynchronous precise c) synchronous imprecise d) asynchronous imprecise
View Answer Answer: c Explanation: The synchronous imprecise is usually not supported on the PowerPC architecture and also in the MPC601, MPC603 etc.



51 - Question

Which exceptions are used in the PowerPC for floating point? a) synchronous imprecise b) asynchronous imprecise c) synchronous precise d) synchronous imprecise
View Answer Answer: a Explanation: The PowerPC can handle the floating point exception by making use of the synchronous imprecise mode.



52 - Question

Which exception is used in the external interrupts and decrementer-caused exceptions? a) synchronous precise b) asynchronous precise c) synchronous imprecise d) asynchronous imprecise
View Answer Answer: b Explanation: The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can occur at any time within the instruction flow.



53 - Question

Which exception can be masked by clearing the EE bit to zero in the MSR? a) synchronous imprecise b) synchronous precise c) asynchronous imprecise d) asynchronous precise
View Answer Answer: d Explanation: The asynchronous precise type exceptions can be masked by clearing the EE bits in the MSR. This bit is automatically cleared to zero in the MSR in order to prevent this interrupt causing an exception while other exceptions are being processed.



54 - Question

MCQs on RISC Exceptions-II
Which of the following can be done to ensure that all interrupts are recognised?
a) reset pin
b) external ready pin
c) handshaking
d) acknowledgment
View Answer Answer: c
Explanation: The exception handler performs some kind of handshaking to ensure that all the interrupts are recognised.



55 - Question

How many types of exceptions are associated with the asynchronous imprecise?
a) 1
b) 2
c) 3
d) 4
View Answer Answer: b
Explanation: Two types of exceptions are associated with the asynchronous imprecise. These are system reset and machine checks.



56 - Question

How is the internal registers and memories are reset?
a) system reset
b) memory reset
c) peripheral reset
d) software reset
View Answer Answer: a
Explanation: By doing the system reset, all the current processing are stopped and the internal registers and the memories are reset. advertisement



57 - Question

How is the machine check exception is taken in an asynchronous imprecise?
a) ME bit
b) EE bit
c) FE0
d) FE1
View Answer Answer: a
Explanation: The machine check exception is taken only if the ME bit of the MSR is set. If it is cleared, the processor will enter into a check stop state.



58 - Question

Which of the following are the exceptions associated with the asynchronous imprecise?
a) decrementer interrupt
b) machine check
c) instruction dependent
d) external interrupt
View Answer Answer: b
Explanation: The machine check and the system reset are two types of exceptions which are associated with the asynchronous imprecise.



59 - Question

Which of the following possesses an additional priority?
a) asynchronous precise
b) asynchronous imprecise
c) synchronous precise
d) synchronous imprecise
View Answer Answer: c
Explanation: The synchronous precise exceptions provide additional priority because it is possible for an instruction to generate more than one exception.



60 - Question

Which of the following has more priority?
a) system reset
b) machine check
c) external interrupt
d) decrementer interrupt
View Answer Answer: a
Explanation: The system reset has the first priority then comes the machine reset, next priority moves for the instruction dependent, and the next priority is an external interrupt, and last priority level goes for the decrementer interrupt.



61 - Question

Which bit controls the external interrupts and the decrementer exceptions?
a) FE1
b) FE0
c) EE
d) ME
View Answer Answer: c
Explanation: The EE bit in the MSR controls the external interrupts and the decrementer exceptions.



62 - Question

Which bit controls the machine check exceptions?
a) ME
b) FE0
c) FE1
d) EE
View Answer Answer: a
Explanation: The ME bit in the MSR controls the machine check interrupts.



63 - Question

Which bits control the floating point exceptions?
a) EE
b) FE0
c) FE1
d) both FE1 and FE2
View Answer Answer: d
Explanation: The FE0 and FE1 control the floating point exceptions.



64 - Question

Which of the following is a 16 kbyte block?
a) register
b) vector table
c) buffer
d) lookaside buffer
View Answer Answer: b
Explanation: The vector table is a 16 kbyte block which is divided into 256 byte divisions in which each division is allocated for particular exceptions and it also contains the handler routine associated with the exceptions.



65 - Question

MCQs on Fast Interrupts
Which processors use fast interrupts?
a) DSP processor
b) RISC processor
c) CISC processor
d) Harvard processor
View Answer Answer: a
Explanation: The fast interrupts are used in the DSP processors or in microcontrollers in which a small routine is executed without saving the context of the processor.



66 - Question

Which interrupts generate fast interrupt exception?
a) internal interrupt
b) external interrupt
c) software interrupt
d) hardware interrupt
View Answer Answer: b
Explanation: The external interrupts generates the fast interrupt routine exception in which the external interrupt is synchronised with the processor clock.



67 - Question

What is the disadvantage of the fast interrupts?
a) stack frame
b) delay
c) size of routine
d) low speed
View Answer Answer: c
Explanation: The disadvantages associated with the fast interrupt is the size of routine which can be executed and the resources allocated. In this technique, it allocates a couple of address registers for the fast interrupt routine. advertisement



68 - Question

Which of the following does not have a stack frame building?
a) hardware interrupt
b) software interrupt
c) non-maskable interrupt
d) fast interrupt
View Answer Answer: d
Explanation: The fast interrupt does not have stack frame building and it does not possess any such delays. This can be considered as the advantage of the fast interrupts.



69 - Question

What is programmed to generate a two instruction fast interrupt?
a) software
b) application
c) timer
d) sensor
View Answer Answer: c
Explanation: The SCI timer generates the two instruction fast interrupt. This increment the register R1.



70 - Question

Which of the following can auto increment the register R1?
a) SCI timer
b) interrupt
c) software interrupt
d) non-maskable interrupt
View Answer Answer: a
Explanation: The SCI timer is used to generate the two instruction fast interrupt that can increment the register R1 which acts as a simple counter.



71 - Question

Which of the following forces a standard service routine?
a) READY interrupt
b) IRQA interrupt
c) NMI
d) software interrupt
View Answer Answer: b
Explanation: The SCI timer is used to generate the two instruction fast interrupt which increments the register R1 that acts as a simple counter which times the period between the events. The events itself generates an IRQA interrupt, that forces the service routine.



72 - Question

Which of the following can be used as a reset button?
a) NMI
b) internal interrupt
c) external interrupt
d) software interrupt
View Answer Answer: a
Explanation: The non-maskable interrupt is used to generate an interrupt to try and recover control and therefore, the NMI can be used as a reset button.



73 - Question

Which of the following is connected to a fault detection circuit?
a) internal interrupt
b) external interrupt
c) NMI
d) software interrupt
View Answer Answer: c
Explanation: The non-maskable interrupt is used to generate an interrupt which can be connected to a fault detection circuit like watchdog timer or parity checker.

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