Engineering Questions with Answers - Multiple Choice Questions

MCQs on Internal Architecture of 80286

1 - Question

The CPU of 80286 contains
a) 16-bit general purpose registers
b) 16-bit segment registers
c) status and control register
d) all of the mentioned

View Answer

Answer: d
Explanation: The CPU of 80286 contains the same set of registers as in 8086.




2 - Question

The bits that are modified according to the result of the execution of logical and arithmetic instructions are called
a) byte addressable bit
b) control flag bits
c) status flag bit
d) none of the mentioned

View Answer

Answer: c
Explanation: The flag register bits, D0, D2, D4, D6, D7 and D11 are modified according to the result of the execution of logical and arithmetic instructions. These are called as status flag bits.




3 - Question

The flags that are used for controlling machine operation are called
a) status flags
b) control flags
c) machine controlled flags
d) all of the mentioned

View Answer
Answer: b
Explanation: The flags such as trap flag (TF) and Interrupt flag (IF) bits are used for controlling the machine operation, and thus they are called control flags.
 



4 - Question

The additional field that is available in 80286 is
a) I/O Privilege field
b) nested task flag
c) protection enable
d) all of the mentioned

View Answer

Answer: d
Explanation: The additional fields available in 80286 flag register are, I/O Privilege field, nested task flag, protection enable, and monitor processor extension.




5 - Question

Which of the block is not considered as a block of an architecture of 80286?
a) address unit
b) bus unit
c) instruction unit
d) control unit

View Answer

Answer: d
Explanation: The CPU may be viewed to contain four functional parts and they are
i) Address Unit
ii) Bus Unit
iii) Instruction Unit
iv) Execution Unit.




6 - Question

The unit that is responsible for calculating the address of instructions, and data that the CPU wants to access is
a) bus unit
b) address unit
c) instruction unit
d) control unit

View Answer

Answer: b
Explanation: The address unit is responsible for calculating the address of instructions, and data that the CPU wants to access. Also, the address lines derived by this unit may be used to address different peripherals.




7 - Question

The process of fetching the instructions in advance, and storing in the queue is called
a) mapping
b) swapping
c) instruction pipelining
d) storing

View Answer

Answer: c
Explanation: The instructions are fetched in advance and stored in a queue to enable faster execution of the instructions. This concept is known as instruction pipelining.




8 - Question

The CPU must flush out the prefetched instructions immediately following the branch instruction in
a) conditional branch
b) unconditional branch
c) conditional and unconditional branches
d) none of the mentioned

View Answer

Answer: b
Explanation: In case of unconditional branch, the CPU will have to flush out the prefetched instructions, immediately following the branch instruction.




9 - Question

The device that interfaces and control the internal data bus with the system bus is
a) data interface
b) controller interface
c) data and control interface
d) data transreceiver

View Answer

Answer: d
Explanation: The data transreceivers interface and control the internal data bus with the system bus.




10 - Question

The register bank of Execution Unit of 80286 is used as
a) for storing data
b) scratch pad
c) special purpose registers
d) all of the mentioned

View Answer

Answer: d
Explanation: The execution unit contains the register bank, used for storing the data as scratch pad, or used as special purpose registers.




11 - Question

Which of the following is not an interrupt generated by 80286?
a) software interrupts
b) hardware or external interrupts
c) INT instruction
d) none of the mentioned

View Answer
Answer: d
Explanation: The interrupts generated by 80286 may be divided into 3 categories as external or hardware interrupts, INT instruction or software interrupts and interrupts generated by exceptions.



12 - Question

For which of the following instruction does the return address point to instruction causing an exception?
a) divide error exception
b) bound range exceeded exception
c) invalid opcode exception
d) all of the mentioned

View Answer

Answer: d
Explanation: For the instructions, divide error, bound range exceeded and invalid opcode exceptions, the return address points to the instruction causing exception.




13 - Question

The instruction that comes into action, if the trap flag is set is
a) maskable interrupt
b) non-maskable interrupt
c) single step interrupt
d) breakpoint interrupt

View Answer

Answer: c
Explanation: Single step interrupt is an internal interrupt that comes into action if the trap flag (TF) is set.




14 - Question

The interrupt that has the highest priority among the following is
a) Single step
b) NMI (non-maskable interrupt)
c) INTR
d) Instruction exception

View Answer

Answer: d
Explanation: The instruction exception has the highest priority followed by single step, NMI and INTR instrution.




15 - Question

The interrupt that has the lowest priority among the following is
a) Processor extension segment overrun
b) INTR
c) INT instruction
d) NMI

View Answer

Answer: c
Explanation: The INT instruction has the lowest priority. The order of priority of interrupts from high to low is
1) instruction exception
2) single step
3) NMI
4) processor extension segment overrun
5) INTR
6) INT instruction.

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