Engineering Questions with Answers - Multiple Choice Questions
MCQs on Implementing Embedded System: Hardware/Software Codesign
1 - Question
MCQs on Introduction to Software and Hardware Implementation
Which of the following allows the reuse of the software and the hardware components?
a) platform based design
b) memory design
c) peripheral design
d) input design
View Answer
Explanation: The platform design allows the reuse of the software and the hardware components in order to cope with the increasing complexity in the design of embedded systems.
2 - Question
Which of the following is the design in which both the hardware and software are considered during the design?
a) platform based design
b) memory based design
c) software/hardware codesign
d) peripheral design
View Answer
Explanation: The software/hardware codesign is the one which having both hardware and software design concerns. This will help in the right combination of the hardware and the software for the efficient product.
3 - Question
What does API stand for?
a) address programming interface
b) application programming interface
c) accessing peripheral through interface
d) address programming interface
View Answer
Explanation: The platform-based design helps in the reuse of both the hardware and the software components. The application programming interface helps in extending the platform towards software applications. advertisement
4 - Question
Which activity is concerned with identifying the task at the final embedded systems?
a) high-level transformation
b) compilation
c) scheduling
d) task-level concurrency management
View Answer
Explanation: There are many design activities associated with the platforms in the embedded system and one such is the task-level concurrency management which helps in identifying the task that needed to be present in the final embedded systems.
5 - Question
In which design activity, the loops are interchangeable?
a) compilation
b) scheduling
c) high-level transformation
d) hardware/software partitioning
View Answer
Explanation: The high-level transformation is responsible for the high optimizing transformations, that is, the loops can be interchanged so that the accesses to array components become more local.
6 - Question
Which design activity helps in the transformation of the floating point arithmetic to fixed point arithmetic?
a) high-level transformation
b) scheduling
c) compilation
d) task-level concurrency management
View Answer
Explanation: The high-level transformation are responsible for the high optimizing transformations, that is, for the loop interchanging and the transformation of the floating point arithmetic to the fixed point arithmetic can be done by the high-level transformation.
7 - Question
Which design activity is in charge of mapping operations to hardware?
a) scheduling
b) high-level transformation
c) hardware/software partitioning
d) compilation
View Answer
Explanation: The hardware/software partitioning is the activity which is in charge of mapping operations to the software or to the hardware.
8 - Question
Which of the following is approximated during hardware/software partitioning, during task-level concurrency management?
a) scheduling
b) compilation
c) task-level concurrency management
d) high-level transformation
View Answer
Explanation: The scheduling is performed in several contexts. It should be approximated with the other design activities like the compilation, hardware/software partitioning, and task-level concurrency management. The scheduling should be precise for the final code.
9 - Question
Which of the following is a process of analyzing the set of possible designs?
a) design space exploration
b) scheduling
c) compilation
d) hardware/software partitioning
View Answer
Explanation: The design space exploration is the process of analyzing the set of designs and the design which meet the specification is selected.
10 - Question
Which of the following is a meet-in-the-middle approach?
a) peripheral based design
b) platform based design
c) memory based design
d) processor design
View Answer
Explanation: The platform is an abstraction layer which covers many possible refinements to a lower level and is mainly follows a meet-in-the-middle approach.
11 - Question
MCQs on High Level Optimization
What does FRIDGE stand for?
a) fixed-point programming design environment
b) floating-point programming design environment
c) fixed-point programming decoding
d) floating-point programming decoding
View Answer
Explanation: Certain tools are available which are developed for the optimization programmes and one such tool is the FRIDGE or fixed-point programming design environment, commercially made by Synopsys System Studio.
12 - Question
Which of the following tool can replace the floating point arithmetic to fixed point arithmetic?
a) SDS
b) FAT
c) VFAT
d) FRIDGE
View Answer
Explanation: There are certain tools available which are developed for the optimization programmes and one such tool is the FRIDGE or fixed-point programming design environment, commercially made available by Synopsys System Studio. This tool can is used in the transformation program, that is the conversion of floating point arithmetic to the fixed point arithmetic. This is widely used in signal processing.
13 - Question
Which programming algorithm is used in the starting process of the FRIDGE?
a) C++
b) JAVA
c) C
d) BASIC
View Answer
Explanation: The FRIDGE tool uses C programming algorithm in the initial stage and is converted to a fixed-C algorithm which extends C by two extends. advertisement
14 - Question
In which loop transformation, a single loop is split into two?
a) loop tiling
b) loop fusion
c) loop permutation
d) loop unrolling
View Answer
Explanation: Many loop transformation are done for the optimization of the program and one such loop transformation is the loop fusion in which a single loop is split and the loop fission includes the merging of the two separate loops.
15 - Question
Which loop transformations have several instances of the loop body?
a) loop fusion
b) loop unrolling
c) loop fission
d) loop tiling
View Answer
Explanation: The loop unrolling is a standard transformation which creates several instances of the loop body and the number of copies of the loop is known as the unrolling factor.
16 - Question
The number of copies of a loop is called as
a) rolling factor
b) loop factor
c) unrolling factor
d) loop size
View Answer
Explanation: The number of copies of the loop is known as the unrolling factor and it is a standard transformation that produces instances of the loop body.
17 - Question
Which of the following can reduce the loop overhead and thus increase the speed?
a) loop unrolling
b) loop tiling
c) loop permutation
d) loop fusion
View Answer
Explanation: The loop unrolling can reduce the loop overhead, that is the fewer branches per execution of the loop body, which in turn increases the speed but is only restricted to loops with a constant number of iteration. The unrolling can increase the code size.
18 - Question
Which loop transformation can increase the code size?
a) loop permutation
b) loop fusion
c) loop fission
d) loop unrolling
View Answer
Explanation: The loop unrolling can decrease the loop overhead, the fewer branches per execution of the loop body and this can increase the speed but is only restricted to loops with a constant number of iteration and thus the loop unrolling can increase the code size.
19 - Question
Which memories are faster in nature?
a) RAM
b) ROM
c) Scratch pad memories
d) EEPROM
View Answer
Explanation: As the memory size decreases, it is faster in operation, that is the smaller memories are faster than the larger memories. The small memories are caches and the scratch pad memories.
20 - Question
Which loop transformation reduces the energy consumption of the memory systems?
a) loop permutation
b) loop tiling
c) loop fission
d) loop fusion
View Answer
Explanation: The loop tiling can reduce the energy the consumption of the memory systems.
21 - Question
MCQs on Hardware or Software Partitioning
What does COOL stand for?
a) coprocessor tool
b) codesign tool
c) code tool
d) code control
View Answer
Explanation: The COOL is the codesign tool which is one of the optimisation technique for partitioning the software and the hardware.
22 - Question
How many inputs part does COOL have?
a) 2
b) 4
c) 5
d) 3
View Answer
Explanation: The codesign tool consists of three input parts. These are target technology, design constraints and the behaviour and each input follows different functions. The target technology comprises the information about the different hardware platform components available within the system, design constraints are the second part of the input which contains the design constraints, and the behaviour part is the third input which describes the required overall behaviour.
23 - Question
Which part of the COOL input comprises information about the available hardware platform components?
a) target technology
b) design constraints
c) both behaviour and design constraints
d) behaviour
View Answer
Explanation: The codesign tool consists of three input parts which are described as target technology, design constraints and the behavior. Each input does different functions. The target technology comprises information about the different hardware platform components available within the system.
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24 - Question
What does the second part of the COOL input comprise?
a) behaviour and target technology
b) design constraints
c) behaviour
d) target technology
View Answer
Explanation: The second part of the COOL input comprises of the design constraints such as the latency, maximum memory size, required throughput or maximum area for application-specific hardware.
25 - Question
What does the third part of the COOL input comprise?
a) design constraints and target technology
b) design constraints
c) behaviour
d) target technology
View Answer
Explanation: The codesign tool consists of three input parts and the third part of the COOL input describes the overall behaviour of the system. The hierarchical task graphs are used for this.
26 - Question
How many edges does the COOL use?
a) 1
b) 2
c) 3
d) 4
View Answer
Explanation: The codesign tool has 2 edges. These are timing edges and the communication edges. The timing edge provides the timing constraints whereas the communication edge contains the information about the amount of information to be exchanged.
27 - Question
Which edge provides the timing constraints?
a) timing edge
b) communication edge
c) timing edge and communication edge
d) special edge
View Answer
Explanation: The codesign tool has 2 edges. They are timing edges and the communication edges. The timing edge provides the timing constraints.
28 - Question
Which edge of the COOL contains information about the amount of information to be exchanged?
a) regular edge
b) timing edge
c) communication edge
d) special edge
View Answer
Explanation: The codesign tool has 2 edges and these are timing edges and the communication edges. The communication edge contains information about the amount of information to be exchanged.
29 - Question
What does Index set KH denotes?
a) processor
b) hardware components
c) task graph nodes
d) task graph node type
View Answer
Explanation: There is a certain index set which is used in the IP or the integer programming model. The KH denotes the hardware component types.
30 - Question
What does Index set L denotes?
a) processor
b) task graph node
c) task graph node type
d) hardware components
View Answer
Explanation: The index set is used in the IP or the integer programming model. The Index set KP denotes the processor, I denote the task graph nodes and the L denotes the task graph node type.
31 - Question
MCQs on Compilers
Which of the following helps in reducing the energy consumption of the embedded system?
a) compilers
b) simulator
c) debugger
d) emulator
View Answer
Explanation: The compilers can reduce the energy consumption of the embedded system and the compilers performing the energy optimizations are available.
32 - Question
Which of the following help to meet and prove real-time constraints?
a) simulator
b) debugger
c) emulator
d) compiler
View Answer
Explanation: There are several reasons for designing the optimization and compilers and one such is that it could help to meet and prove the real-time constraints.
33 - Question
Which of the following is an important ingredient of all power optimization?
a) energy model
b) power model
c) watt model
d) power compiler
View Answer
Explanation: Saving energy can be done at any stage of the embedded system development. The high-level optimization techniques can reduce power consumption and similarly compiler optimization also can reduce the power consumption and the most important thing in power optimization are the power model. advertisement
34 - Question
Who proposed the first power model?
a) Jacome
b) Russell
c) Tiwari
d) Russell and Jacome
View Answer
Explanation: Tiwari proposed the first power model in the year 1974. The model includes the so-called bases and the inter-instruction instructions. Base costs of the instruction correspond to the energy consumed per instruction execution when an infinite sequence of that instruction is executed. Inter instruction costs model the additional energy consumed by the processor if instructions change.
35 - Question
Who proposed the third power model?
a) Tiwari
b) Russell
c) Jacome
d) Russell and Jacome
View Answer
Explanation: The third model was proposed by Russell and Jacome in the year 1998.
36 - Question
Which compiler is based on the precise measurements of two fixed configurations?
a) first power model
b) second power model
c) third power model
d) fourth power model
View Answer
Explanation: The third model was proposed by Russell and Jacome in the year 1998 and is based on the precise measurements of the two fixed configurations.
37 - Question
What does SPM stand for?
a) scratch pad memories
b) sensor parity machine
c) scratch pad machine
d) sensor parity memories
View Answer
Explanation: The smaller memories provide faster access and consume less energy per access and SPM or scratch pad memories is a kind of small memory which access fastly and consume less energy per access and it can be exploited by the compiler.
38 - Question
Which model is based on precise measurements using real hardware?
a) encc energy-aware compiler
b) first power model
c) third power model
d) second power model
View Answer
Explanation: The encc-energy aware compiler uses the energy model by Steinke et al. it is based on the precise measurements of the real hardware. The power consumption of the memory, as well as the processor, is included in this model.
39 - Question
What is the solution to the knapsack problem?
a) many-to-many mapping
b) one-to-many mapping
c) many-to-one mapping
d) one-to-one mapping
View Answer
Explanation: The knapsack problem is associated with the size constraints, that is the size of the scratch pad memories. This problem can be solved by one-to-one mapping which was presented in an integer programming model by Steinke et al.
40 - Question
How can one compute the power consumption of the cache?
a) Lee power model
b) First power model
c) Third power model
d) CACTI
View Answer
Explanation: The CACTI can compute the power consumption of the cache which is proposed by Wilton and Jouppi in the year 1996.