Engineering Questions with Answers - Multiple Choice Questions

MCQs on Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design Issues of RISC Processors -2

1 - Question

The number of CPIs(Clock Per Instruction) for an instruction of RISC processors is
a) 0
b) 1
c) 2
d) 3

View Answer

Answer: b
Explanation: RISC processors have unity CPI(Clock Per Instruction), which is due to the optimization of each instruction on the CPU and massive pipelining embedded in a RISC processor.




2 - Question

Which of the following is not true about RISC processors?
a) addressing modes are less
b) pipelining is key for high speed
c) microcoding is required
d) single machine cycle instructions

View Answer

Answer: c
Explanation: Unlike the CISC, in RISC architecture, instruction microcoding is not required.




3 - Question

The RISC processors that support variable length instructions are from
a) Intel
b) Motorola
c) AMD
d) Intel and Motorola

View Answer

Answer: d
Explanation: In RISC, each instruction is of the same length, so that it may be fetched in a single operation. The traditional microprocessors from Intel or Motorola support variable length instructions.




4 - Question

Which of the following is true about register windowing?
a) chips expose 32 registers to programmer
b) puts demands on multiplexers
c) puts enormous demands on register ports
d) all of the mentioned

View Answer
Answer: d
Explanation: The register windowing involves a mechanism where the chips expose 32 registers to the programmer at any one time. It puts enormous demands on multiplexers and register ports to make any physical register appear to be any logical register.

 




5 - Question

The disadvantage of register windowing is
a) high speed
b) puts demands on multiplexers/register ports
c) consumes less cycles
d) doesn’t handle overflow/underflow

View Answer

Answer: d
Explanation: It is impossible to predict when the register file will overflow or underflow, so performance is unpredictable. It generates a software fault, which the operating system has to handle, consuming more cycles.




6 - Question

The register window is used to point the number of physical registers is
a) infinite
b) that are currently used
c) finite
d) that are unused

View Answer

Answer: c
Explanation: The register window only helps us to point the number of physical registers is finite.




7 - Question

Which of the following is not a stage of pipeline of a RISC processor?
a) read registers and decode the instructions
b) fetch instructions from registers
c) write result into a register
d) access an operand in data memory

View Answer

Answer: b
Explanation: There are 5 stages in pipelining. They are
1. Fetch instructions from memory
2. Read registers and decode the instructions
3. Execute the instructions or calculate an address
4. Access an operand in data memory
5. Write result into a register.




8 - Question

When an instruction depends on the results of the previous instructions then
a) error occurs
b) software fault occurs
c) data dependency occurs
d) hardware fault occurs

View Answer

Answer: c
Explanation: A data dependency occurs when an instruction depends on the results of the previous instructions.




9 - Question

The instructions that instruct the processor to make a decision about the next instruction to be executed are
a) data dependency instructions
b) branch instructions
c) control transfer instructions
d) none

View Answer

Answer: b
Explanation: The branch instructions are those which instruct the processor to make a decision about the next instruction to be executed, depending upon whether the condition is satisfied or not.




10 - Question

The reason for which the RISC processor goes to idle state(or stall) is
a) delay in reading information from memory
b) poor instruction set design
c) dependencies between instructions
d) all of the mentioned

View Answer

Answer: d
Explanation: There are a variety of reasons, including delays in reading information from memory, poor instruction set design, or dependencies between instructions for the RISC processor to remain idle.

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